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Giuk Kim

Publications and source records attributed to Giuk Kim.

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Probabilistic Tree Inference Enabled by FDSOI Ferroelectric FETs

Artificial intelligence applications in autonomous driving, medical diagnostics, and financial systems increasingly demand machine learning models that can provide robust uncertainty quantification, interpretability, and noise resilience. Bayesian decision trees (BDTs) are attractive for these tasks because they combine probabilistic reasoning, interpretable decision-making, and robustness to noise. However, existing hardware implementations of BDTs based on CPUs and GPUs are limited by memory bottlenecks and irregular processing patterns, while multi-platform solutions exploiting analog content-addressable memory (ACAM) and Gaussian random number generators (GRNGs) introduce integration complexity and energy overheads. Here we report a monolithic FDSOI-FeFET hardware platform that natively supports both ACAM and GRNG functionalities. The ferroelectric polarization of FeFETs enables compact, energy-efficient multi-bit storage for ACAM, and band-to-band tunneling in the gate-to-drain overlap region and subsequent hole storage in the floating body provides a high-quality entropy source for GRNG. System-level evaluations demonstrate that the proposed architecture provides robust uncertainty estimation, interpretability, and noise tolerance with high energy efficiency. Under both dataset noise and device variations, it achieves over 40% higher classification accuracy on MNIST compared to conventional decision trees. Moreover, it delivers more than two orders of magnitude speedup over CPU and GPU baselines and over four orders of magnitude improvement in energy efficiency, making it a scalable solution for deploying BDTs in resource-constrained and safety-critical environments.

cs.ET

Vertical NAND in a Ferroelectric-driven Paradigm Shift

Over the past decades, the relentless scaling and mass production of flash memory have underpinned the data-centric era. Yet charge-trap-based 3D NAND flash is now constrained by intrinsic physical and architectural limits, including reliability degradation at the device level, high operating power at the array level, and vertical scaling saturation at the system level. These bottlenecks hinder further advances in storage density and energy efficiency required by memory-centric computing. This Perspective outlines how coupling ferroelectric polarization with charge trapping can reconfigure the foundations of flash memory. In these hybrid architectures, polarization offers an energy-efficient pathway for charge modulation through enhanced Fowler-Nordheim tunneling, while trapped charges reinforce polarization-driven states to ensure stability. Such synergistic dynamics enable low-voltage operation and integration beyond one thousand layers without compromising process compatibility. We discuss the material, device, and architectural transitions required to realize this hybrid technology and chart future research directions to overcome the remaining scaling bottlenecks. Hybrid ferroelectric NAND extends conventional flash toward a scalable and energy-efficient platform, marking a paradigm shift for next-generation non-volatile memory.

physics.app-ph