Towards Efficient Verification of Computation in Quantum Devices
Designing quantum processors is a complex task that demands advanced verification methods to ensure their correct functionality. However, traditional methods of comprehensively verifying quantum devices, such as quantum process tomography, face significant limitations because of the exponential growth in computational resources. These limitations arise from treating the system as a black box and ignoring its design structure. Consequently, new testing methods must be developed considering the design structure. In this paper, we investigate the structure of computations on the hardware, focusing on the layered interruptible quantum circuit model and designing a scalable algorithm to verify it comprehensively. Specifically, for a given quantum hardware that claims to process an unknown $n$ qubit $d$ layer circuit via a finite set of quantum gates, our method completely reconstructs the circuits within a time complexity of $O(d^2 t \log (n/\delta))$, guaranteeing success with a probability of at least $1-\delta$. Here, $t$ represents the maximum execution time for each circuit layer. Our approach significantly reduces execution time for completely verifying computations in quantum devices, achieving double logarithmic scaling in the problem size. Furthermore, we validate our algorithm through experiments using IBM's quantum cloud service, demonstrating its potential applicability in the noisy intermediate-scale quantum era.