Harish Batchu | Searcharxiv

arXiv2025

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education

While most instruction set architectures (ISAs) are only available to use through the purchase of a restrictive commercial license, the RISC-V ISA presents a free and open-source alternative. Due to this availability, many free and open-source implementations have been developed and can be accessed on platforms such as GitHub. If an open source, easy-to-use, and robust RISC-V implementation could be obtained, it could be easily adapted for pedagogical and amateur use. In this work we accomplish three goals in relation to this outlook. First, we propose a set of criteria for evaluating the components of a RISC-V implementation's ecosystem from a pedagogical perspective. Second, we analyze a number of existing open-source RISC-V implementations to determine how many of the criteria they fulfill. We then develop a comprehensive solution that meets all of these criterion and is released open-source for other instructors to use. The framework is developed in a composable way that it's different components can be disaggregated per individual course needs. Finally, we also report on a limited study of student feedback.

cs.AR↗

arXiv2023

IPU: Flexible Hardware Introspection Units

Modern chip designs are increasingly complex, making it difficult for developers to glean meaningful insights about hardware behavior while real workloads are running. Hardware introspection aims to solve this by enabling the hardware itself to observe and report on its internal operation - especially in the field, where the chip is executing real-world software and workloads. Three key problems are now imminent that hardware introspection can solve: A/B testing of hardware in the field, obfuscated hardware, and obfuscated software which prevents chip designers from gleaning insights on in the field behavior of their chips. To this end, the goal is to enable monitoring chip hardware behavior in the field, at real-time speeds with no slowdowns, with minimal power overheads, and thereby obtain insights on chip behavior and workloads. This paper implements the system architecture for and introduces the Introspection Processing Unit (IPU) - one solution to said goal. We perform case studies exemplifying the application of hardware introspection to the three problems through an IPU and implement an RTL level prototype. Across the case studies, we show that an IPU with area overhead less than 1 percent at 7nm, and overall power consumption of less than 25 mW is able to create previously inconceivable analysis: evaluating instruction prefetchers in the field before deployment, creating per-instruction cycles stacks of arbitrary programs, and detailing fine-grained cycle-by-cycle utilization of hardware modules.

cs.AR↗