arXiv subjects

Hritom Das

Publications and source records attributed to Hritom Das.

7 recordsLinked to original sources

arXiv2026

SPORT: Spherical-PSNR-Optimized tRuncaTion for Power-Efficient 360-Degree Video Systems

Memory bandwidth accounts for 30-40% of total power consumption in standalone virtual reality (VR) headsets, yet existing systems typically store the entire 360-degree frame at a uniform resolution regardless of viewer gaze. This paper presents SPORT (Spherical-PSNR Optimized tRuncaTion), a bit-truncation framework that reduces display-path memory power by storing only the most significant bits of pixels outside the user's field of view (FoV). Specifically, a new bit-truncation framework is developed to use weighted-to-spherically-uniform PSNR (WS-PSNR) directly in the optimization constraint, eliminating the metric inconsistency that arises when standard PSNR is used for a WS-PSNR quality target. Also, gaze-predictive tile classification compensates for the 9.33 ms end-to-end pipeline latency, reducing boundary misclassifications by 5.2 percentage points at a cost of only 0.01 ms. In addition, the developed SPORT-B variant, which keeps the FoV lossless, achieves 47.9% memory power saving and 47.9% bandwidth reduction across different 4K video sequences while satisfying all three per-region WS-PSNR thresholds and maintaining SSIM = 1.000 in the attended region. The full adaptive variant SPORT-A reaches 51.6% power saving, 3.1percentage points more than a PSNR-based optimizer at equal measured quality. SPORT is validated on the TrunMEM360 flexible SRAM Application-Specific Integrated Circuit (ASIC) fabricated in SkyWater 130 nm CMOS, confirming byte-exact silicon-software agreement, with WS-PSNR and SSIM matching within 0.1 dB and 0.001. CACTI-based analysis confirms 48.72% DRAM leakage reduction and 36.4%/36.7% read/write energy reduction. The total motion-to-photon latency of 9.33 ms satisfies the 20 ms VR comfort budget with a 53.3% safety margin.

cs.AR↗

arXiv2025

Vibe2Spike: Batteryless Wireless Tags for Vibration Sensing with Event Cameras and Spiking Networks

The deployment of dense, low-cost sensors is critical for realizing ubiquitous smart environments. However, existing sensing solutions struggle with the energy, scalability, and reliability trade-offs imposed by battery maintenance, wireless transmission overhead, and data processing complexity. In this work, we present Vibe2Spike, a novel battery-free, wireless sensing framework that enables vibration-based activity recognition using visible light communication (VLC) and spiking neural networks (SNNs). Our system uses ultra-low-cost tags composed only of a piezoelectric disc, a Zener diode, and an LED, which harvest vibration energy and emit sparse visible light spikes without requiring batteries or RF radios. These optical spikes are captured by event cameras and classified using optimized SNN models evolved via the EONS framework. We evaluate Vibe2Spike across five device classes, achieving 94.9\% average classification fitness while analyzing the latency-accuracy trade-offs of different temporal binning strategies. Vibe2Spike demonstrates a scalable, and energy-efficient approach for enabling intelligent environments in a batteryless manner.

eess.SP↗

arXiv2025

In-Sensor Motion Recognition with Memristive System and Light Sensing Surfaces

In this paper, we introduce a novel device architecture that merges memristive devices with light-sensing surfaces, for energy-efficient motion recognition at the edge. Our light-sensing surface captures motion data through in-sensor computation. This data is then processed using a memristive system equipped with a HfO2-based synaptic device, coupled with a winner-take-all (WTA) circuit, tailored for low-power motion classification tasks. We validate our end-to-end system using four distinct human hand gestures - left-to-right, right-to-left, bottom-to-top, and top-to-bottom movements - to assess energy efficiency and classification robustness. Our experiments show that the system requires an average of only 4.17 nJ for taking our processed analog signal and mapping weights onto our memristive system and 0.952 nJ for testing per movement class, achieving 97.22% accuracy even under 5% noise interference. A key advantage of our proposed architecture is its low energy requirement, enabling the integration of energy-harvesting solutions such as solar power for sustainable autonomous operation. Additionally, our approach enhances data privacy by processing data locally, reducing the need for external data transmission and storage.

cs.HC↗

arXiv2024

Two Birds with One Stone: Differential Privacy by Low-power SRAM Memory

The software-based implementation of differential privacy mechanisms has been shown to be neither friendly for lightweight devices nor secure against side-channel attacks. In this work, we aim to develop a hardware-based technique to achieve differential privacy by design. In contrary to the conventional software-based noise generation and injection process, our design realizes local differential privacy (LDP) by harnessing the inherent hardware noise into controlled LDP noise when data is stored in the memory. Specifically, the noise is tamed through a novel memory design and power downscaling technique, which leads to double-faceted gains in privacy and power efficiency. A well-round study that consists of theoretical design and analysis and chip implementation and experiments is presented. The results confirm that the developed technique is differentially private, saves 88.58% system power, speeds up software-based DP mechanisms by more than 10^6 times, while only incurring 2.46% chip overhead and 7.81% estimation errors in data recovery.

cs.CR↗

arXiv2023

Optimizations for a Current-Controlled Memristor-based Neuromorphic Synapse Design

The synapse is a key element of neuromorphic computing in terms of efficiency and accuracy. In this paper, an optimized current-controlled memristive synapse circuit is proposed. Our proposed synapse demonstrates reliability in the face of process variation and the inherent stochastic behavior of memristors. Up to an 82% energy optimization can be seen during the SET operation over prior work. In addition, the READ process shows up to 54% energy savings. Our current-controlled approach also provides more reliable programming over traditional programming methods. This design is demonstrated with a 4-bit memory precision configuration. Using a spiking neural network (SNN), a neuromorphic application analysis was performed with this precision configuration. Our optimized design showed up to 82% improvement in control applications and a 2.7x improvement in classification applications compared with other design cases.

cs.ET↗

arXiv2023

An Efficient and Accurate Memristive Memory for Array-based Spiking Neural Networks

Memristors provide a tempting solution for weighted synapse connections in neuromorphic computing due to their size and non-volatile nature. However, memristors are unreliable in the commonly used voltage-pulse-based programming approaches and require precisely shaped pulses to avoid programming failure. In this paper, we demonstrate a current-limiting-based solution that provides a more predictable analog memory behavior when reading and writing memristive synapses. With our proposed design READ current can be optimized by about 19x compared to the 1T1R design. Moreover, our proposed design saves about 9x energy compared to the 1T1R design. Our 3T1R design also shows promising write operation which is less affected by the process variation in MOSFETs and the inherent stochastic behavior of memristors. Memristors used for testing are hafnium oxide based and were fabricated in a 65nm hybrid CMOS-memristor process. The proposed design also shows linear characteristics between the voltage applied and the resulting resistance for the writing operation. The simulation and measured data show similar patterns with respect to voltage pulse-based programming and current compliance-based programming. We further observed the impact of this behavior on neuromorphic-specific applications such as a spiking neural network

cs.NE↗

arXiv2023

Enhanced Read Resolution in Reconfigurable Memristive Synapses for Spiking Neural Networks

Synapse is a key element of any neuromorphic computing system which is mostly constructed with memristor devices. A memristor is a two-terminal analog memory device. Memristive synapse suffers from various challenges such as forming at high voltage, SET, RESET failure, and READ margin or resolution issue between two weights. Enhanced READ resolution is very important to make a memristive synapse functionally reliable. Usually, the READ resolution is very small for a memristive synapse with 4-bit data precision. This work considers a step-by-step analysis to enhance the READ current resolution for a current-controlled memristor-based synapse. An empirical model is used to characterize the HfO2-based memristive device. 1st and 2nd stage device of our proposed synapse can be scaled to enhance the READ current margin up to ~ 4.3x and ~ 21% respectively. Moreover, READ current resolution can be enhanced with run-time adaptation features such as READ voltage scaling and body biasing. The READ voltage scaling and body biasing can improve the READ current resolution by about 46% and 15% respectively. TENNLabs' neuromorphic computing framework is leveraged to evaluate the effect of READ current resolution on classification applications. Higher READ current resolution shows better accuracy than lower resolution with different percentages of read noise scenarios.

cs.ET↗