arXiv subjects

Huiyang Zhou

Publications and source records attributed to Huiyang Zhou.

At least 19 recordsLinked to original sources

arXiv2026

Efficient Magic State Factory Via Transversal Non-Clifford Gate

Magic-state preparation is a central component of fault-tolerant quantum computing. Recent theoretical and experimental successes in code-switch-based magic-state preparation have underscored the promise of these methods for quantum error correction. Similarly, magic-state cultivation has likewise been demonstrated in both numerical and experimental settings. However, a thorough comparison between magic-state cultivation and code-switch-based magic-state factories is still missing. In this work, we carry out end-to-end simulations of magic-state preparation using code switching and compare its resource requirements and performance against magic-state cultivation. As part of this analysis, we develop a lattice-surgery protocol for transfer between the doubled color code and the rotated surface code. We extend the complete code-switching protocol to the $d=5$ doubled color code and perform the corresponding end-to-end simulations. Finally, we propose two fault-tolerant magic-state preparation protocols that combine phase-kickback checks with a transversal non-Clifford gate.

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arXiv2026

TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing

Ray tracing (RT) is a 3D graphics technique that offers highly realistic visuals. It is becoming prominent and accessible as GPU vendors have integrated dedicated ray tracing acceleration hardware. However, tracing millions of rays through 3D scenes consisting of high numbers of triangles in real time is challenging and requires expensive hardware. The main bottleneck in RT workloads is the expensive Bounding Volume Hierarchy (BVH) traversal task, which is a large tree structure that encodes the 3D scene. BVH traversal is a memory-bound problem, as the GPU threads spend most of their time reading tree node data from memory. In this work, we attack the memory latency bottleneck of ray tracing through prefetching. We propose a novel hardware prefetcher, named Tree Traversal Prefetcher (TTP), for ray tracing. The main idea is to leverage the existing tree traversal stack in the RT units for highly accurate prefetching. In particular, TTP prefetches nodes using the addresses already available on the hardware traversal stacks of each thread. For DFS (Depth-first search) based traversal, prefetches are generated when nodes are being popped consecutively from the traversal stack, potentially corresponding to upward traversal through the tree. We evaluate TTP on a cycle-level simulator, Vulkan-sim 2.0, and show that it achieves 1.48x speedup on average (up to 1.89x) compared to the baseline, with nearly negligible hardware overhead. TTP achieves 98.92% average L1 accuracy, which is the ratio of the prefetched blocks being actually referenced by demand loads. The coverage, computed as the ratio of L1 miss reduction over baseline L1 misses, is 31.54%, correlating well with the achieved speedup.

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arXiv2026

Scalable Qumode-Qubit State Transfer and Fast-forward Quantum Fourier Transform using Oscillators

Transferring the information stored in the expansion coefficients of a multi-qubit state to the coefficients of a continuous-variable state is an important protocol for communicating quantum information. It was shown in previous work how to transfer an $n$-qubit state to a single qumode in $\mathcal{O}(2^n)$ time. We show that by transferring this state to $m$ qumodes, the runtime can be improved to $\mathcal{O}(2^{n/m})$. Furthermore, we demonstrate how multi-qumode state transfer can be used as a subroutine for approximately realizing the $n$-qubits quantum Fourier transform on $m$-qumode with runtime scaling $\mathcal{O}(m2^{n/m}/ε+m^2)$, accelerating qubit quantum Fourier transform using qumodes. This work presents a scalable approach to convert discrete and continuous quantum information between an arbitrary number of qubits and qumodes. It represents a crucial step forward in mixed analog-digital quantum signal processing for computing, sensing, and communication.

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arXiv2026

HyQBench: A Benchmark Suite for Hybrid CV-DV Quantum Computing

Hybrid continuous-variable (CV)-discrete-variable (DV) quantum systems present a promising direction for quantum computing by combining the high dimensional encoding capabilities of qumodes with the control offered by DV qubits on the coupled qumodes. There have been exciting recent progresses on hybrid CV-DV quantum computing, including variational algorithms, error correction, compiler-level optimizations for Hamiltonian simulation, etc. However, there is a lack of a standardized CV-DV benchmark suite for assessing various emerging hardware platforms and evaluating software optimizations on hybrid CV-DV circuits. In this work, we introduce a simulation and benchmarking framework for hybrid CV-DV circuits, implemented using Bosonic Qiskit-a tool specifically designed to model CV-DV systems, along with QuTip for functional correctness verification. We construct and characterize representative CV-DV benchmarks, including cat state generation, GKP state generation, CV-DV state transfers, hybrid quantum Fourier transform, variational quantum algorithms, Hamiltonian simulation, and Shor's algorithm. To assess circuit complexity and scalability, we define a feature map organized into two categories: general features (e.g., qubit/qumode count, gate counts) and CV-DV-specific features (e.g., Wigner negativity, energy, truncation cost). These metrics enable evaluation of both classical simulability and hardware resource requirements. Our results, including one benchmark on real hardware, demonstrate that hybrid CV-DV architectures are not only viable but well-suited for a range of computational tasks, from optimization to Hamiltonian simulation. This framework lays the groundwork for systematic evaluation and future development of hybrid quantum systems.

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arXiv2025

Q-Cluster: Quantum Error Mitigation Through Noise-Aware Unsupervised Learning

Quantum error mitigation (QEM) is critical in reducing the impact of noise in the pre-fault-tolerant era, and is expected to complement error correction in fault-tolerant quantum computing (FTQC). In this paper, we propose a novel QEM approach, Q-Cluster, that uses unsupervised learning (clustering) to reshape the measured bit-string distribution. Our approach starts with a simplified bit-flip noise model. It first performs clustering on noisy measurement results, i.e., bit-strings, based on the Hamming distance. The centroid of each cluster is calculated using a qubit-wise majority vote. Next, the noisy distribution is adjusted with the clustering outcomes and the bit-flip error rates using Bayesian inference. Our simulation results show that Q-Cluster can mitigate high noise rates (up to 40% per qubit) with the simple bit-flip noise model. However, real quantum computers do not fit such a simple noise model. To address the problem, we (a) apply Pauli twirling to tailor the complex noise channels to Pauli errors, and (b) employ a machine learning model, ExtraTrees regressor, to estimate an effective bit-flip error rate using a feature vector consisting of machine calibration data (gate & measurement error rates), circuit features (number of qubits, numbers of different types of gates, etc.) and the shape of the noisy distribution (entropy). Our experimental results show that our proposed Q-Cluster scheme improves the fidelity by a factor of 1.46x, on average, compared to the unmitigated output distribution, for a set of low-entropy benchmarks on five different IBM quantum machines. Our approach outperforms the state-of-art QEM approaches M3 [24], Hammer [35], and QBEEP [33] by 1.29x, 1.47x, and 2.65x, respectively.

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arXiv2025

A Quantum Network Processor Unit for Distributed Quantum Computing

As quantum computing progresses, the need for scalable solutions to address large-scale computational problems has become critical. Quantum supercomputers are the next upcoming frontier by enabling multiple quantum processors to collaborate effectively to solve large-scale computational problems. The emergence of quantum supercomputers necessitates an efficient interface to manage the quantum communication protocols between quantum processors. In this paper, we propose the Quantum Network Processing Unit (QNPU), which enables quantum applications to efficiently scale beyond the capacity of individual quantum processors, serving as a critical building block for future quantum supercomputers. The QNPU works alongside the Quantum Processing Unit (QPU) in our decoupled processing units architecture, where the QPU handles local quantum operations while the QNPU manages quantum communication between nodes. We design a comprehensive instruction set architecture (ISA) for the QNPU with high-level communication protocol abstractions, implemented via micro-operations that manage EPR resources, quantum operations, and classical communication. To facilitate programming, we introduce DistQASM, which extends OpenQASM with distributed quantum operations. We then propose a microarchitecture featuring both scalar and superscalar QNPU designs to enhance performance for communication-intensive quantum workloads. Finally, we evaluate the performance of our proposed QNPU design with distributed quantum workloads and demonstrate that the QNPU significantly improves the efficiency of communication between quantum nodes, paving the way for quantum supercomputing.

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arXiv2025

A Flower-Inspired Solution for Computer Memory Wear-Leveling

Lengthening a computer memory's lifespan is important for e-waste and sustainability. Uneven wear of memory is a major barrier. The problem is becoming even more urgent as emerging memory such as phase-change memory is subject to even shorter lifespan. Various solutions have been proposed, but they either require complicated hardware extensions or apply only to certain program constructs such as loops. This research proposes a new method, dual-ring wear leveling. It takes inspiration from the natural law known as the ``golden ratio" and how it helps flower petals evenly receive sun lights. By modeling memory as two rings and combines the idea with existing memory management, garbage collection, the new solution offers an effective way to reduce memory wear and hence lengthen memory lifespan. It is deterministic, able to automatically adapt to memory size, requiring no hardware changes, and adding no slowdown to program executions.

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arXiv2025

Hybrid continuous-discrete-variable quantum computing: a guide to utility

Quantum computing has traditionally centered around the discrete variable paradigm. A new direction is the inclusion of continuous variable modes and the consideration of a hybrid continuous-discrete approach to quantum computing. In this paper, we discuss some of the advantages of this modality, and lay out a number of potential applications that can make use of it; these include applications from physics, chemistry, and computer science. We also briefly overview some of the algorithmic and software considerations for this new paradigm.

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arXiv2025

LLM-Powered Code Analysis and Optimization for Gaussian Splatting Kernels

3D Gaussian splatting (3DGS) is a transformative technique with profound implications on novel view synthesis and real-time rendering. Given its importance, there have been many attempts to improve its performance. However, with the increasing complexity of GPU architectures and the vast search space of performance-tuning parameters, it is a challenging task. Although manual optimizations have achieved remarkable speedups, they require domain expertise and the optimization process can be highly time consuming and error prone. In this paper, we propose to exploit large language models (LLMs) to analyze and optimize Gaussian splatting kernels. To our knowledge, this is the first work to use LLMs to optimize highly specialized real-world GPU kernels. We reveal the intricacies of using LLMs for code optimization and analyze the code optimization techniques from the LLMs. We also propose ways to collaborate with LLMs to further leverage their capabilities. For the original 3DGS code on the MipNeRF360 datasets, LLMs achieve significant speedups, 19% with Deepseek and 24% with GPT-5, demonstrating the different capabilities of different LLMs. By feeding additional information from performance profilers, the performance improvement from LLM-optimized code is enhanced to up to 42% and 38% on average. In comparison, our best-effort manually optimized version can achieve a performance improvement up to 48% and 39% on average, showing that there are still optimizations beyond the capabilities of current LLMs. On the other hand, even upon a newly proposed 3DGS framework with algorithmic optimizations, Seele, LLMs can still further enhance its performance by 6%, showing that there are optimization opportunities missed by domain experts. This highlights the potential of collaboration between domain experts and LLMs.

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arXiv2025

Genesis: A Compiler Framework for Hamiltonian Simulation on Hybrid CV-DV Quantum Computers

This paper introduces Genesis, the first compiler designed to support Hamiltonian Simulation on hybrid continuous-variable (CV) and discrete-variable (DV) quantum computing systems. Genesis is a two-level compilation system. At the first level, it decomposes an input Hamiltonian into basis gates using the native instruction set of the target hybrid CV-DV quantum computer. At the second level, it tackles the mapping and routing of qumodes/qubits to implement long-range interactions for the gates decomposed from the first level. Rather than a typical implementation that relies on SWAP primitives similar to qubit-based (or DV-only) systems, we propose an integrated design of connectivity-aware gate synthesis and beamsplitter SWAP insertion tailored for hybrid CV-DV systems. We also introduce an OpenQASM-like domain-specific language (DSL) named CVDV-QASM to represent Hamiltonian in terms of Pauli-exponentials and basic gate sequences from the hybrid CV-DV gate set. Genesis has successfully compiled several important Hamiltonians, including the Bose-Hubbard model, $\mathbb{Z}_2-$Higgs model, Hubbard-Holstein model, Heisenberg model and Electron-vibration coupling Hamiltonians, which are critical in domains like quantum field theory, condensed matter physics, and quantum chemistry. Our implementation is available at Genesis-CVDV-Compiler(https://github.com/ruadapt/Genesis-CVDV-Compiler).

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arXiv2024

BoostCom: Towards Efficient Universal Fully Homomorphic Encryption by Boosting the Word-wise Comparisons

Fully Homomorphic Encryption (FHE) allows for the execution of computations on encrypted data without the need to decrypt it first, offering significant potential for privacy-preserving computational operations. Emerging arithmetic-based FHE schemes (ar-FHE), like BGV, demonstrate even better performance in word-wise comparison operations over non-arithmetic FHE (na-FHE) schemes, such as TFHE, especially for basic tasks like comparing values, finding maximums, and minimums. This shows the universality of ar-FHE in effectively handling both arithmetic and non-arithmetic operations without the expensive conversion between arithmetic and non-arithmetic FHEs. We refer to universal arithmetic Fully Homomorphic Encryption as uFHE. The arithmetic operations in uFHE remain consistent with those in the original arithmetic FHE, which have seen significant acceleration. However, its non-arithmetic comparison operations differ, are slow, and have not been as thoroughly studied or accelerated. In this paper, we introduce BoostCom, a scheme designed to speed up word-wise comparison operations, enhancing the efficiency of uFHE systems. BoostCom involves a multi-prong optimizations including infrastructure acceleration (Multi-level heterogeneous parallelization and GPU-related improvements), and algorithm-aware optimizations (slot compaction, non-blocking comparison semantic). Together, BoostCom achieves an end-to-end performance improvement of more than an order of magnitude (11.1x faster) compared to the state-of-the-art CPU-based uFHE systems, across various FHE parameters and tasks.

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arXiv2024

QuTracer: Mitigating Quantum Gate and Measurement Errors by Tracing Subsets of Qubits

Quantum error mitigation plays a crucial role in the current noisy-intermediate-scale-quantum (NISQ) era. As we advance towards achieving a practical quantum advantage in the near term, error mitigation emerges as an indispensable component. One notable prior work, Jigsaw, demonstrates that measurement crosstalk errors can be effectively mitigated by measuring subsets of qubits. Jigsaw operates by running multiple copies of the original circuit, each time measuring only a subset of qubits. The localized distributions yielded from measurement subsetting suffer from less crosstalk and are then used to update the global distribution, thereby achieving improved output fidelity. Inspired by the idea of measurement subsetting, we propose QuTracer, a framework designed to mitigate both gate and measurement errors in subsets of qubits by tracing the states of qubit subsets throughout the computational process. In order to achieve this goal, we introduce a technique, qubit subsetting Pauli checks (QSPC), which utilizes circuit cutting and Pauli Check Sandwiching (PCS) to trace the qubit subsets distribution to mitigate errors. The QuTracer framework can be applied to various algorithms including, but not limited to, VQE, QAOA, quantum arithmetic circuits, QPE, and Hamiltonian simulations. In our experiments, we perform both noisy simulations and real device experiments to demonstrate that QuTracer is scalable and significantly outperforms the state-of-the-art approaches.

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arXiv2024

Tetris: A Compilation Framework for VQA Applications in Quantum Computing

Quantum computing has shown promise in solving complex problems by leveraging the principles of superposition and entanglement. Variational quantum algorithms (VQA) are a class of algorithms suited for near term quantum computers due to their modest requirements of qubits and depths of computation. This paper introduces Tetris, a compilation framework for VQA applications on near term quantum devices. Tetris focuses on reducing two qubit gates in the compilation process since a two qubit gate has an order of magnitude more significant error and execution time than a single qubit gate. Tetris exploits unique opportunities in the circuit synthesis stage often overlooked by the state of the art VQA compilers for reducing the number of two qubit gates. Tetris comes with a refined IR of Pauli string to express such a two qubit gate optimization opportunity. Moreover, Tetris is equipped with a fast bridging approach that mitigates the hardware mapping cost. Overall, Tetris demonstrates a reduction of up to 41.3 percent in CNOT gate counts, 37.9 percent in circuit depth, and 42.6 percent in circuit duration for various molecules of different sizes and structures compared with the state-of-the-art approaches. Tetris is open-sourced at this link.

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arXiv2024

Maximum Likelihood Quantum Error Mitigation for Algorithms with a Single Correct Output

Quantum error mitigation is an important technique to reduce the impact of noise in quantum computers. With more and more qubits being supported on quantum computers, there are two emerging fundamental challenges. First, the number of shots required for quantum algorithms with large numbers of qubits needs to increase in order to obtain a meaningful distribution or expected value of an observable. Second, although steady progress has been made in improving the fidelity of each qubit, circuits with a large number of qubits are likely to produce erroneous results. This low-shot, high-noise regime calls for highly scalable error mitigation techniques. In this paper, we propose a simple and effective mitigation scheme, qubit-wise majority vote, for quantum algorithms with a single correct output. We show that our scheme produces the maximum likelihood (ML) estimate under certain assumptions, and bound the number of shots required. Our experimental results on real quantum devices confirm that our proposed approach requires fewer shots than existing ones, and can sometimes recover the correct answers even when they are not observed from the measurement results.

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arXiv2023

Dynamic Runtime Assertions in Quantum Ternary Systems

With the rapid advancement of quantum computing technology, there is a growing need for new debugging tools for quantum programs. Recent research has highlighted the potential of assertions for debugging quantum programs. In this paper, we investigate assertions in quantum ternary systems, which are more challenging than those in quantum binary systems due to the complexity of ternary logic. We propose quantum ternary circuit designs to assert classical, entanglement, and superposition states, specifically geared toward debugging quantum ternary programs.

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arXiv2023

Enhancing Virtual Distillation with Circuit Cutting for Quantum Error Mitigation

Virtual distillation is a technique that aims to mitigate errors in noisy quantum computers. It works by preparing multiple copies of a noisy quantum state, bridging them through a circuit, and conducting measurements. As the number of copies increases, this process allows for the estimation of the expectation value with respect to a state that approaches the ideal pure state rapidly. However, virtual distillation faces a challenge in realistic scenarios: preparing multiple copies of a quantum state and bridging them through a circuit in a noisy quantum computer will significantly increase the circuit size and introduce excessive noise, which will degrade the performance of virtual distillation. To overcome this challenge, we propose an error mitigation strategy that uses circuit-cutting technology to cut the entire circuit into fragments. With this approach, the fragments responsible for generating the noisy quantum state can be executed on a noisy quantum device, while the remaining fragments are efficiently simulated on a noiseless classical simulator. By running each fragment circuit separately on quantum and classical devices and recombining their results, we can reduce the noise accumulation and enhance the effectiveness of the virtual distillation technique. Our strategy has good scalability in terms of both runtime and computational resources. We demonstrate our strategy's effectiveness through noisy simulation and experiments on a real quantum device.

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arXiv2023

Folding-Free ZNE: A Comprehensive Quantum Zero-Noise Extrapolation Approach for Mitigating Depolarizing and Decoherence Noise

Quantum computers in the NISQ era are prone to noise. A range of quantum error mitigation techniques has been proposed to address this issue. Zero-noise extrapolation (ZNE) stands out as a promising one. ZNE involves increasing the noise levels in a circuit and then using extrapolation to infer the zero noise case from the noisy results obtained. This paper presents a novel ZNE approach that does not require circuit folding or noise scaling to mitigate depolarizing and/or decoherence noise. To mitigate depolarizing noise, we propose leveraging the extreme/infinite noisy case, which allows us to avoid circuit folding. Specifically, the circuit output with extreme noise becomes the maximally mixed state. We show that using circuit-reliability metrics, simple linear extrapolation can effectively mitigate depolarizing noise. With decoherence noise, different states decay into the all-zero state at a rate that depends on the number of excited states and time. Therefore, we propose a state- and latency-aware exponential extrapolation that does not involve folding or scaling. When dealing with a quantum system affected by both decoherence and depolarizing noise, we propose to use our two mitigation techniques in sequence: first applying decoherence error mitigation, followed by depolarizing error mitigation. A common limitation of ZNE schemes is that if the circuit of interest suffers from high noise, scaling-up noise levels could not provide useful data for extrapolation. We propose using circuit-cut techniques to break a large quantum circuit into smaller sub-circuits to overcome this limitation. This way, the noise levels of the sub-circuits are lower than the original circuit, and ZNE can become more effective in mitigating their noises.

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arXiv2022

Not All SWAPs Have the Same Cost: A Case for Optimization-Aware Qubit Routing

Despite rapid advances in quantum computing technologies, the qubit connectivity limitation remains to be a critical challenge. Both near-term NISQ quantum computers and relatively long-term scalable quantum architectures do not offer full connectivity. As a result, quantum circuits may not be directly executed on quantum hardware, and a quantum compiler needs to perform qubit routing to make the circuit compatible with the device layout. During the qubit routing step, the compiler inserts SWAP gates and performs circuit transformations. Given the connectivity topology of the target hardware, there are typically multiple qubit routing candidates. The state-of-the-art compilers use a cost function to evaluate the number of SWAP gates for different routes and then select the one with the minimum number of SWAP gates. After qubit routing, the quantum compiler performs gate optimizations upon the circuit with the newly inserted SWAP gates. In this paper, we observe that the aforementioned qubit routing is not optimal, and qubit routing should \textit{not} be independent on subsequent gate optimizations. We find that with the consideration of gate optimizations, not all of the SWAP gates have the same basis-gate cost. These insights lead to the development of our qubit routing algorithm, NASSC (Not All Swaps have the Same Cost). NASSC is the first algorithm that considers the subsequent optimizations during the routing step. Our optimization-aware qubit routing leads to better routing decisions and benefits subsequent optimizations. We also propose a new optimization-aware decomposition for the inserted SWAP gates. Our experiments show that the routing overhead compiled with our routing algorithm is reduced by up to $69.30\%$ ($21.30\%$ on average) in the number of CNOT gates and up to $43.50\%$ ($7.61\%$ on average) in the circuit depth compared with the state-of-the-art scheme, SABRE.

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