arXiv subjects

Igor Stolichnov

Publications and source records attributed to Igor Stolichnov.

5 recordsLinked to original sources

arXiv2026

Alternative origins of polarity in compressively strained SrTiO3-RENiO3 capacitors

Since its original prediction 25 years ago, room-temperature out-of-plane ferroelectricity in compressively strained SrTiO3 remains an ongoing pursuit. In this work, we investigate the structural, electrical and electromechanical properties of highly strained epitaxial SrTiO3 capacitors with rare earth nickelate electrodes. The SrTiO3 layers experience compressive strains up to -3% and exhibit pronounced tetragonality, comparable to that of bulk PbTiO3. Variable-temperature electrical measurements and room-temperature piezoresponse force microscopy reveal butterfly-shaped capacitance-voltage hysteresis and domain-like electromechanical response typical of ferroelectric materials. However, the overall behavior is inconsistent with a stable ferroelectric state. We therefore propose an alternative mechanism for the observed polarity in our samples based on spatially inhomogeneous internal fields. Our first-principles calculations show that such fields may arise from charge discontinuities between the formally charged NdNiO3 layers and charge-neutral SrTiO3 layers.

cond-mat.mtrl-sci↗

arXiv2026

Monolithically Integrated VO$_2$ Mott Oscillators for Energy-Efficient Spiking Neurons

Brain-inspired non-Boolean computing and sensing enable energy-efficient, error-tolerant, and highly parallel information processing, yet their deployment remains limited by the lack of compact, scalable spiking hardware. Mott phase-transition materials offer a promising route because their abrupt insulator-to-metal transitions enable neuron-like thresholding and oscillations. Among them, vanadium dioxide (VO$_2$) is particularly attractive owing to its near-room-temperature transition, fast switching, and scalability. However, existing VO$_2$ neuristors rely on discrete components, limiting integration density. Here, we report monolithic back-end-of-the-line (BEOL) integration of one-transistor-one-VO$_2$-memristor (1T-1MR) spiking neurons on a CMOS-compatible platform. VO$_2$ nanosheets are fabricated by pulsed-laser deposition atop dielectrically isolated silicon-on-insulator (SOI) p-type junctionless field-effect transistors (JLFETs) below 430 $^\circ$C. The architecture exhibits gate-tunable oscillations from 40 to 410 kHz in 60 nm-thin VO$_2$ devices with a 6 $\mu$m$^2$ active area, achieving 18 pJ per spike and 8 $\mu$W at room temperature, with potential for sub-3 $\mu$W operation. We uncover a non-monotonic dependence of oscillation frequency on bias current and temperature and analyze bias-dependent stochastic firing, revealing the nonlinear physics of integrated VO$_2$ thin-film memristors. Finally, we demonstrate voltage-controlled oscillator functionality and on-chip resistive coupling between two nano-oscillators mediated by a JLFET. These results establish a pathway toward dense, energy-efficient, monolithically integrated Mott neuromorphic hardware compatible with future computing and spiking sensing systems.

eess.SY↗

arXiv2025

CMOS-compatible vanadium dioxide via Pulsed Laser and Atomic Layer deposition: towards ultra-thin film phase-change layers

Vanadium dioxide, a well-known Mott insulator, is a highly studied electronic material with promising applications in information processing and storage. While fully crystalline layers exhibit exceptional properties, such as a sharp and abrupt conductivity change at the metal-insulator transition, fabricating poly-crystalline films on silicon substrates often involves trade-offs in transport characteristics and switching performance, especially for ultra-thin layers required in advanced gate applications. In this study, we explore the growth of vanadium dioxide films on standard wet-oxidized silicon wafers using two established deposition techniques with pulsed laser deposition and atomic layer deposition. Thin films, ranging in thickness from 200 to 10 nano meters, were systematically characterized through structural and electrical analyses to optimize key growth parameters. Temperature and pressure were identified as the primary factors affecting film quality, and the optimal growth conditions across the entire thickness range are discussed in detail. We demonstrate that both pulsed laser deposition and atomic layer deposition methods can successfully produce ultra-thin vanadium dioxide layers down to 8 nano meters with functional properties suitable for practical applications. This work underscores the potential of vanadium dioxide for fully industry compatible phase-change switching devices and provides valuable insights into optimizing growth processes for poly-crystalline films.

cond-mat.mtrl-sci↗

arXiv2018

Negative Capacitance as Digital and Analog Performance Booster for Complementary MOS Transistors

Boltzmann tyranny poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Negative Capacitance (NC) in ferroelectric materials is proposed in order to address this physical limitation of CMOS technology. A polarization destabilization in ferroelectrics causes an effective negative permittivity, resulting in a differential voltage amplification and a reduced subthreshold swing when integrated into the gate stack of a transistor. Recent demonstrations of negative capacitance concerned mainly n-type MOSFETs and their subthreshold slope. An effective technology booster should be capable of improving the performance of both n- and p-type transistors. In this work, we report a significant enhancement in both digital (subthreshold swing, on-current over off-current ratio, and overdrive) and analog (transconductance and current efficiency factor) FoM of commercial 28nm CMOS process by exploiting a PZT capacitor as the negative capacitance booster. Accordingly, a sub-thermal swing down to 10 mV/decade together with an enhanced current efficiency factor up to 10$^5$ V$^{-1}$ is obtained in both n- and p-type MOSFETs at room temperature. The overdrive voltage is enhanced up to 0.45 V, leading to a supply voltage reduction of 50\%.

physics.app-ph↗

arXiv2010

Evidence for dielectric aging due to progressive 180 domain wall pinning in polydomain Pb(Zr0.45Ti0.55)O3 thin films

An evidence that the dielectric ageing in the polydomain Pb(Zr0.45Ti0.55)O3 thin films is controlled by progressive pinning of 180 domain walls is presented. To provide such a conclusion, we use a general method, which is based on the study of the time evolution of the nonlinear, but anhysteretic, dielectric response of the ferroelectric to a weak electric field. A thermodynamic model of the ferroelectric system where the dielectric response is controlled by bending movements of pinned 180 domain walls is developed. Within this model, the nonlinear permittivity of the ferroelectric is expressed as a function of the microstructural parameters of the domain pattern. It is shown that using the analysis of the time evolution of the nonlinear permittivity, it is possible to estimate changes in the concentration of the pinning centers that block the movements of the 180 domain walls during aging in polydomain perovskite ferroelectrics.

cond-mat.mtrl-sci↗