arXiv subjects

Indranil Chakraborty

Publications and source records attributed to Indranil Chakraborty.

33 records · Page 2Linked to original sources

arXiv2020

Memory effects in Kundt wave spacetimes

Memory effects in the exact Kundt wave spacetimes are shown to arise in the behaviour of geodesics in such spacetimes. The types of Kundt spacetimes we consider here are direct products of the form $H^2\times M(1,1)$ and $S^2\times M(1,1)$. Both geometries have constant scalar curvature. We consider a scenario in which initial velocities of the transverse geodesic coordinates are set to zero (before the arrival of the pulse) in a spacetime with non-vanishing background curvature. We look for changes in the separation between pairs of geodesics caused by the pulse. Any relative change observed in the position and velocity profiles of geodesics, after the burst, can be solely attributed to the wave (hence, a memory effect). For constant negative curvature, we find there is permanent change in the separation of geodesics after the pulse has departed. Thus, there is displacement memory, though no velocity memory is found. In the case of constant positive scalar curvature (Plebański-Hacyan spacetimes), we find both displacement and velocity memory along one direction. In the other direction, a new kind of memory (which we term as frequency memory effect) is observed where the separation between the geodesics shows periodic oscillations once the pulse has left. We also carry out similar analyses for spacetimes with a non-constant scalar curvature, which may be positive or negative. The results here seem to qualitatively agree with those for constant scalar curvature, thereby suggesting a link between the nature of memory and curvature.

gr-qc↗

arXiv2020

Conditionally Deep Hybrid Neural Networks Across Edge and Cloud

The pervasiveness of "Internet-of-Things" in our daily life has led to a recent surge in fog computing, encompassing a collaboration of cloud computing and edge intelligence. To that effect, deep learning has been a major driving force towards enabling such intelligent systems. However, growing model sizes in deep learning pose a significant challenge towards deployment in resource-constrained edge devices. Moreover, in a distributed intelligence environment, efficient workload distribution is necessary between edge and cloud systems. To address these challenges, we propose a conditionally deep hybrid neural network for enabling AI-based fog computing. The proposed network can be deployed in a distributed manner, consisting of quantized layers and early exits at the edge and full-precision layers on the cloud. During inference, if an early exit has high confidence in the classification results, it would allow samples to exit at the edge, and the deeper layers on the cloud are activated conditionally, which can lead to improved energy efficiency and inference latency. We perform an extensive design space exploration with the goal of minimizing energy consumption at the edge while achieving state-of-the-art classification accuracies on image classification tasks. We show that with binarized layers at the edge, the proposed conditional hybrid network can process 65% of inferences at the edge, leading to 5.5x computational energy reduction with minimal accuracy degradation on CIFAR-10 dataset. For the more complex dataset CIFAR-100, we observe that the proposed network with 4-bit quantization at the edge achieves 52% early classification at the edge with 4.8x energy reduction. The analysis gives us insights on designing efficient hybrid networks which achieve significantly higher energy efficiency than full-precision networks for edge-cloud based distributed intelligence systems.

cs.LG↗

arXiv2020

IMAC: In-memory multi-bit Multiplication andACcumulation in 6T SRAM Array

`In-memory computing' is being widely explored as a novel computing paradigm to mitigate the well known memory bottleneck. This emerging paradigm aims at embedding some aspects of computations inside the memory array, thereby avoiding frequent and expensive movement of data between the compute unit and the storage memory. In-memory computing with respect to Silicon memories has been widely explored on various memory bit-cells. Embedding computation inside the 6 transistor (6T) SRAM array is of special interest since it is the most widely used on-chip memory. In this paper, we present a novel in-memory multiplication followed by accumulation operation capable of performing parallel dot products within 6T SRAM without any changes to the standard bitcell. We, further, study the effect of circuit non-idealities and process variations on the accuracy of the LeNet-5 and VGG neural network architectures against the MNIST and CIFAR-10 datasets, respectively. The proposed in-memory dot-product mechanism achieves 88.8% and 99% accuracy for the CIFAR-10 and MNIST, respectively. Compared to the standard von Neumann system, the proposed system is 6.24x better in energy consumption and 9.42x better in delay.

cs.ET↗

arXiv2020

GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural Networks

The analog nature of computing in Memristive crossbars poses significant issues due to various non-idealities such as: parasitic resistances, non-linear I-V characteristics of the device etc. The non-idealities can have a detrimental impact on the functionality i.e. computational accuracy of crossbars. Past works have explored modeling the non-idealities using analytical techniques. However, several non-idealities have data dependent behavior. This can not be captured using analytical (non data-dependent) models thereby, limiting their suitability in predicting application accuracy. To address this, we propose a Generalized Approach to Emulating Non-Ideality in Memristive Crossbars using Neural Networks (GENIEx), which accurately captures the data-dependent nature of non-idealities. We perform extensive HSPICE simulations of crossbars with different voltage and conductance combinations. Following that, we train a neural network to learn the transfer characteristics of the non-ideal crossbar. Next, we build a functional simulator which includes key architectural facets such as \textit{tiling}, and \textit{bit-slicing} to analyze the impact of non-idealities on the classification accuracy of large-scale neural networks. We show that GENIEx achieves \textit{low} root mean square errors (RMSE) of $0.25$ and $0.7$ for low and high voltages, respectively, compared to HSPICE. Additionally, the GENIEx errors are $7\times$ and $12.8\times$ better than an analytical model which can only capture the linear non-idealities. Further, using the functional simulator and GENIEx, we demonstrate that an analytical model can overestimate the degradation in classification accuracy by $\ge 10\%$ on CIFAR-100 and $3.7\%$ on ImageNet datasets compared to GENIEx.

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arXiv2020

Geodesic congruences in exact plane wave spacetimes and the memory effect

Displacement and velocity memory effects in the exact, vacuum, plane gravitational wave line element have been studied recently by looking at the behaviour of pairs of geodesics or via geodesic deviation. Instead, one may investigate the evolution of geodesic congruences. In our work here, we obtain the evolution of the kinematic variables which characterise timelike geodesic congruences, using chosen pulse profiles (square and sech-squared) in the exact, plane gravitational wave line element. We also analyse the behaviour of geodesic congruences in possible physical scenarios describable using derivatives (first, second and third) of one of the chosen pulses. Beginning with a discussion on the generic behaviour of such congruences and consequences thereof, we find exact analytical expressions for shear and expansion with the two chosen pulse profiles. Qualitatively similar numerical results are noted when various derivatives of the sech-squared pulse are used. We conclude that for geodesic congruences, a growth (or decay) of shear causes focusing of an initially parallel congruence, after the departure of the pulse. A correlation between the `focusing time (or $u$ value, $u$ being the affine parameter)' and the amplitude of the pulse (or its derivatives) is found. Such features distinctly suggest a memory effect, named in recent literature as ${\cal B}$ memory.

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arXiv2019

Constructing Energy-efficient Mixed-precision Neural Networks through Principal Component Analysis for Edge Intelligence

The `Internet of Things' has brought increased demand for AI-based edge computing in applications ranging from healthcare monitoring systems to autonomous vehicles. Quantization is a powerful tool to address the growing computational cost of such applications, and yields significant compression over full-precision networks. However, quantization can result in substantial loss of performance for complex image classification tasks. To address this, we propose a Principal Component Analysis (PCA) driven methodology to identify the important layers of a binary network, and design mixed-precision networks. The proposed Hybrid-Net achieves a more than 10% improvement in classification accuracy over binary networks such as XNOR-Net for ResNet and VGG architectures on CIFAR-100 and ImageNet datasets while still achieving up to 94% of the energy-efficiency of XNOR-Nets. This work furthers the feasibility of using highly compressed neural networks for energy-efficient neural computing in edge devices.

cs.LG↗

arXiv2019

Discretization based Solutions for Secure Machine Learning against Adversarial Attacks

Adversarial examples are perturbed inputs that are designed (from a deep learning network's (DLN) parameter gradients) to mislead the DLN during test time. Intuitively, constraining the dimensionality of inputs or parameters of a network reduces the 'space' in which adversarial examples exist. Guided by this intuition, we demonstrate that discretization greatly improves the robustness of DLNs against adversarial attacks. Specifically, discretizing the input space (or allowed pixel levels from 256 values or 8-bit to 4 values or 2-bit) extensively improves the adversarial robustness of DLNs for a substantial range of perturbations for minimal loss in test accuracy. Furthermore, we find that Binary Neural Networks (BNNs) and related variants are intrinsically more robust than their full precision counterparts in adversarial scenarios. Combining input discretization with BNNs furthers the robustness even waiving the need for adversarial training for certain magnitude of perturbation values. We evaluate the effect of discretization on MNIST, CIFAR10, CIFAR100 and Imagenet datasets. Across all datasets, we observe maximal adversarial resistance with 2-bit input discretization that incurs an adversarial accuracy loss of just ~1-2% as compared to clean test accuracy.

cs.LG↗

arXiv2019

Efficient Hybrid Network Architectures for Extremely Quantized Neural Networks Enabling Intelligence at the Edge

The recent advent of `Internet of Things' (IOT) has increased the demand for enabling AI-based edge computing. This has necessitated the search for efficient implementations of neural networks in terms of both computations and storage. Although extreme quantization has proven to be a powerful tool to achieve significant compression over full-precision networks, it can result in significant degradation in performance. In this work, we propose extremely quantized hybrid network architectures with both binary and full-precision sections to emulate the classification performance of full-precision networks while ensuring significant energy efficiency and memory compression. We explore several hybrid network architectures and analyze the performance of the networks in terms of accuracy, energy efficiency and memory compression. We perform our analysis on ResNet and VGG network architectures. Among the proposed network architectures, we show that the hybrid networks with full-precision residual connections emerge as the optimum by attaining accuracies close to full-precision networks while achieving excellent memory compression, up to 21.8x in case of VGG-19. This work demonstrates an effective way of hybridizing networks which achieve performance close to full-precision networks while attaining significant compression, furthering the feasibility of using such networks for energy-efficient neural computing in IOT-based edge devices.

cs.LG↗

arXiv2018

A Photonic In-Memory Computing primitive for Spiking Neural Networks using Phase-Change Materials

Spiking Neural Networks (SNNs) offer an event-driven and more biologically realistic alternative to standard Artificial Neural Networks based on analog information processing. This can potentially enable energy-efficient hardware implementations of neuromorphic systems which emulate the functional units of the brain, namely, neurons and synapses. Recent demonstrations of ultra-fast photonic computing devices based on phase-change materials (PCMs) show promise of addressing limitations of electrically driven neuromorphic systems. However, scaling these standalone computing devices to a parallel in-memory computing primitive is a challenge. In this work, we utilize the optical properties of the PCM, Ge\textsubscript{2}Sb\textsubscript{2}Te\textsubscript{5} (GST), to propose a Photonic Spiking Neural Network computing primitive, comprising of a non-volatile synaptic array integrated seamlessly with previously explored `integrate-and-fire' neurons. The proposed design realizes an `in-memory' computing platform that leverages the inherent parallelism of wavelength-division-multiplexing (WDM). We show that the proposed computing platform can be used to emulate a SNN inferencing engine for image classification tasks. The proposed design not only bridges the gap between isolated computing devices and parallel large-scale implementation, but also paves the way for ultra-fast computing and localized on-chip learning.

cs.ET↗

arXiv2018

8T SRAM Cell as a Multi-bit Dot Product Engine for Beyond von-Neumann Computing

Large scale digital computing almost exclusively relies on the von-Neumann architecture which comprises of separate units for storage and computations. The energy expensive transfer of data from the memory units to the computing cores results in the well-known von-Neumann bottleneck. Various approaches aimed towards bypassing the von-Neumann bottleneck are being extensively explored in the literature. Emerging non-volatile memristive technologies have been shown to be very efficient in computing analog dot products in an in-situ fashion. The memristive analog computation of the dot product results in much faster operation as opposed to digital vector in-memory bit-wise Boolean computations. However, challenges with respect to large scale manufacturing coupled with the limited endurance of memristors have hindered rapid commercialization of memristive based computing solutions. In this work, we show that the standard 8 transistor (8T) digital SRAM array can be configured as an analog-like in-memory multi-bit dot product engine. By applying appropriate analog voltages to the read-ports of the 8T SRAM array, and sensing the output current, an approximate analog-digital dot-product engine can be implemented. We present two different configurations for enabling multi-bit dot product computations in the 8T SRAM cell array, without modifying the standard bit-cell structure. Since our proposal preserves the standard 8T-SRAM array structure, it can be used as a storage element with standard read-write instructions, and also as an on-demand analog-like dot product accelerator.

cs.ET↗

arXiv2018

Toward Fast Neural Computing using All-Photonic Phase Change Spiking Neurons

The rapid growth of brain-inspired computing coupled with the inefficiencies in the CMOS implementations of neuromrphic systems has led to intense exploration of efficient hardware implementations of the functional units of the brain, namely, neurons and synapses. However, efforts have largely been invested in implementations in the electrical domain with potential limitations of switching speed, packing density of large integrated systems and interconnect losses. As an alternative, neuromorphic engineering in the photonic domain has recently gained attention. In this work, we demonstrate a purely photonic operation of an Integrate-and-Fire Spiking neuron, based on the phase change dynamics of Ge$_2$Sb$_2$Te$_5$ (GST) embedded on top of a microring resonator, which alleviates the energy constraints of PCMs in electrical domain. We also show that such a neuron can be potentially integrated with on-chip synapses into an all-Photonic Spiking Neural network inferencing framework which promises to be ultrafast and can potentially offer a large operating bandwidth.

cs.ET↗

arXiv2018

Design of a Low Voltage Analog-to-Digital Converter using Voltage Controlled Stochastic Switching of Low Barrier Nanomagnets

The inherent stochasticity in many nano-scale devices makes them prospective candidates for low-power computations. Such devices have been demonstrated to exhibit probabilistic switching between two stable states to achieve stochastic behavior. Recently, superparamagnetic nanomagnets (having low energy barrier EB $\sim$ 1kT) have shown promise of achieving stochastic switching at GHz rates, with very low currents. On the other hand, voltage-controlled switching of nanomagnets through the Magneto-electric (ME) effect has shown further improvements in energy efficiency. In this simulation paper, we first analyze the stochastic switching characteristics of such super-paramagnetic nanomagnets in a voltage-controlled spintronic device. We study the influence of external bias on the switching behavior. Subsequently, we show that our proposed device leverages the voltage controlled stochasticity in performing low-voltage 8-bit analog to digital conversions. This eliminates the need for comparators, unlike the Complementary Metal-Oxide Semiconductor (CMOS)-based flash Analog-to-Digital converters (ADC). This device allows for a simple and compact design which can potentially be applied in implementing sensors which desire low voltage conversions.

cs.ET↗

arXiv2018

Capacitively Driven Global Interconnect with Magnetoelectric Switching Based Receiver for Higher Energy Efficiency

We propose capacitively driven low-swing global interconnect circuit using a receiver that utilizes magnetoelectric (ME) effect induced magnetization switching to reduce the energy consumption. Capacitively driven wire has recently been shown to be effective in improving the performance of global interconnects. Such techniques can reduce the signal swing in the interconnect by using a capacitive divider network and does not require an additional voltage supply. However, the large reduction in signal swing makes it necessary to use differential signaling and amplification for successful regeneration at the receiver, which add area and static power. ME effect induced magnetization reversal has recently been proposed which shows the possibility of using a low voltage to switch a nanomagnet adjacent to a multi-ferroic oxide. Here, we propose an ME effect based receiver that uses the low voltage at the receiving end of the global wire to switch a nanomagnet. The nanomagnet is also used as the free layer of a magnetic tunnel junction (MTJ), the resistance of which is tuned through the ME effect. This change in MTJ resistance is converted to full swing binary signals by using simple digital components. This process allows capacitive low swing interconnection without differential signaling or amplification, which leads to significant energy efficiency. Our simulation results indicate that for 5-10 mm long global wires in IBM 45 nm technology, capacitive ME design consumes 3x lower energy compared to full-swing CMOS design and 2x lower energy compared to differential amplifier based low-swing capacitive CMOS design.

cs.ET↗

arXiv2017

Technology Aware Training in Memristive Neuromorphic Systems based on non-ideal Synaptic Crossbars

The advances in the field of machine learning using neuromorphic systems have paved the pathway for extensive research on possibilities of hardware implementations of neural networks. Various memristive technologies such as oxide-based devices, spintronics and phase change materials have been explored to implement the core functional units of neuromorphic systems, namely the synaptic network, and the neuronal functionality, in a fast and energy efficient manner. However, various non-idealities in the crossbar implementations of the synaptic arrays can significantly degrade performance of neural networks and hence, impose restrictions on feasible crossbar sizes. In this work, we build mathematical models of various non-idealities that occur in crossbar implementations such as source resistance, neuron resistance and chip-to-chip device variations and analyze their impact on the classification accuracy of a fully connected network (FCN) and convolutional neural network (CNN) trained with standard training algorithm. We show that a network trained under ideal conditions can suffer accuracy degradation as large as 59.84% for FCNs and 62.4% for CNNs when implemented on non-ideal crossbars for relevant non-ideality ranges. This severely constrains the sizes for crossbars. As a solution, we propose a technology aware training algorithm which incorporates the mathematical models of the non-idealities in the standard training algorithm. We demonstrate that our proposed methodology achieves significant recovery of testing accuracy within 1.9% of the ideal accuracy for FCNs and 1.5% for CNNs. We further show that our proposed training algorithm can potentially allow the use of significantly larger crossbar arrays of sizes 784$\times$500 for FCNs and 4096$\times$512 for CNNs with a minor or no trade-off in accuracy

cs.ET↗

arXiv2017

Energy-Efficient Memories using Magneto-Electric Switching of Ferromagnets

Voltage driven magneto-electric (ME) switching of ferro-magnets has shown potential for future low-energy spintronic memories. In this paper, we first analyze two different ME devices viz. ME-MTJ and ME-XNOR device with respect to writability, readability and switching speed. Our analysis is based on a coupled magnetization dynamics and electron transport model. Subsequently, we show that the decoupled read/write path of ME-MTJs can be utilized to construct an energy-efficient dual port memory. Further, we also propose a novel content addressable memory (CAM) exploiting the compact XNOR operation enabled by ME-XNOR device.

cs.ET↗