arXiv subjects

Ioannis Savidis

Publications and source records attributed to Ioannis Savidis.

5 recordsLinked to original sources

arXiv2026

Hybrid ASIC-FPAA Fabric for Performance Security Trade-off

In this paper, a hybrid architecture that combines an application specific integrated circuit (ASIC) and a field-programmable analog array (ASIC-FPAA) is proposed to address the performance-security trade-off in analog circuits. A programmable transistor pair (TP) is developed that obfuscates the topology of an analog circuit within an array of transistor pairs while minimizing the degradation in circuit performance due to the implemented security features. In addition, a technique that utilizes dummy transistor pairs is proposed that further masks the topology of a circuit by obfuscating the number of active transistors that comprise the target analog circuit. A method to obfuscate the entire topology of an analog circuit is also developed. The FPAA provides the highest-level of security robustness as the entire circuit topology is programmed onto the transistor pair array, while trading-off performance. For large analog circuits requiring multiple configurable analog blocks (CABs), an algorithm is developed that identifies and maps the sub-blocks of the circuit best suited for obfuscation on the FPAA fabric, while accounting for the trade-off between performance and security. For the delta-sigma modulator, the comparator module is selected for implementation on the FPAA fabric, which results in a reduction of less than 0.25% in the effective number of bits (ENOB) and an increase of 28.1% in the power consumption as compared to an unobfuscated delta-sigma modulator. The security robustness of the proposed techniques are evaluated against the latest attack methodologies. Results indicate that the proposed techniques provide a 5x improvement in security as measured by a developed metric without compromising performance.

cs.AR↗

arXiv2026

EDA-Schema-V2: A Multimodal Schema, Open Datasets, and Benchmarks for Machine Learning in Digital Physical Design

The continuous scaling of CMOS technology has significantly increased the complexity of very large-scale integrated circuits, driving interest in applying machine learning (ML) to electronic design automation (EDA). However, the limited availability of open and standardized datasets limits interoperability, comparability, and reproducibility in ML-based research. This paper introduces EDA-Schema-V2, an open multimodal schema that provides a structured framework for representing and analyzing datasets in digital physical design. The schema includes representations of physical attributes and quality-of-results metrics across multiple stages of the design flow, including logic synthesis, floorplanning, placement, clock network synthesis, and routing. Utilizing the SkyWater 130nm, Nangate 45nm, IHP SG13G2 130nm, and ASAP 7nm open-source process design kits with the OpenROAD tool flow, datasets of physical circuit designs from the IWLS'05 benchmark suite are generated and analyzed. The dataset comprises 7,776 design instances spanning 18 benchmark circuits and includes stage-resolved representations from synthesis through detailed routing, generated through parameter sweeps over clock period, core utilization, and aspect ratio. The dataset contains over 275 million gates, 75 million nets, and more than 36 million extracted timing paths. In addition, twelve representative prediction tasks spanning timing, power, area, and routing metrics are identified, along with baseline analyses that characterize stage-to-stage predictability across the design flow. The resulting datasets and baselines are publicly released to support reproducible ML research and establish standardized benchmarks for evaluating ML-based approaches in digital physical design.

cs.AR↗

arXiv2025

Emerging ML-AI Techniques for Analog and RF EDA

This survey explores the integration of machine learning (ML) into EDA workflows for analog and RF circuits, addressing challenges unique to analog design, which include complex constraints, nonlinear design spaces, and high computational costs. State-of-the-art learning and optimization techniques are reviewed for circuit tasks such as constraint formulation, topology generation, device modeling, sizing, placement, and routing. The survey highlights the capability of ML to enhance automation, improve design quality, and reduce time-to-market while meeting the target specifications of an analog or RF circuit. Emerging trends and cross-cutting challenges, including robustness to variations and considerations of interconnect parasitics, are also discussed.

cs.AR↗

arXiv2025

Deep Representation Learning for Electronic Design Automation

Representation learning has become an effective technique utilized by electronic design automation (EDA) algorithms, which leverage the natural representation of workflow elements as images, grids, and graphs. By addressing challenges related to the increasing complexity of circuits and stringent power, performance, and area (PPA) requirements, representation learning facilitates the automatic extraction of meaningful features from complex data formats, including images, grids, and graphs. This paper examines the application of representation learning in EDA, covering foundational concepts and analyzing prior work and case studies on tasks that include timing prediction, routability analysis, and automated placement. Key techniques, including image-based methods, graph-based approaches, and hybrid multimodal solutions, are presented to illustrate the improvements provided in routing, timing, and parasitic prediction. The provided advancements demonstrate the potential of representation learning to enhance efficiency, accuracy, and scalability in current integrated circuit design flows.

cs.LG↗

arXiv2022

Adaptive-Gravity: A Defense Against Adversarial Samples

This paper presents a novel model training solution, denoted as Adaptive-Gravity, for enhancing the robustness of deep neural network classifiers against adversarial examples. We conceptualize the model parameters/features associated with each class as a mass characterized by its centroid location and the spread (standard deviation of the distance) of features around the centroid. We use the centroid associated with each cluster to derive an anti-gravity force that pushes the centroids of different classes away from one another during network training. Then we customized an objective function that aims to concentrate each class's features toward their corresponding new centroid, which has been obtained by anti-gravity force. This methodology results in a larger separation between different masses and reduces the spread of features around each centroid. As a result, the samples are pushed away from the space that adversarial examples could be mapped to, effectively increasing the degree of perturbation needed for making an adversarial example. We have implemented this training solution as an iterative method consisting of four steps at each iteration: 1) centroid extraction, 2) anti-gravity force calculation, 3) centroid relocation, and 4) gravity training. Gravity's efficiency is evaluated by measuring the corresponding fooling rates against various attack models, including FGSM, MIM, BIM, and PGD using LeNet and ResNet110 networks, benchmarked against MNIST and CIFAR10 classification problems. Test results show that Gravity not only functions as a powerful instrument to robustify a model against state-of-the-art adversarial attacks but also effectively improves the model training accuracy.

cs.LG↗