arXiv subjects

Issam Damaj

Publications and source records attributed to Issam Damaj.

At least 19 recordsLinked to original sources

arXiv2020

High-speed KATAN Ciphers on-a-Chip

Security in embedded systems has become a main requirement in modern electronic devices. The demand for low-cost and highly secure cryptographic algorithms is increasingly growing in fields such as mobile telecommunications, handheld devices, etc. In this paper, we analyze and evaluate the development of cheap and relatively fast hardware implementations of the KATAN family of block ciphers. KATAN is a family of six hardware oriented block ciphers. All KATAN ciphers share an 80-bit key and have 32, 48, or 64-bit blocks. We use VHDL under Altera Quartus in conjunction with ModelSim to implement and analyze our hardware designs. The developed designs are mapped onto high-performance Field Programmable Gate Arrays. We compare our findings with similar hardware implementations and C software versions of the algorithms. The performance analysis of the C implementations is done using Intel Vtune Amplifier running on Dell precision T7500 with its dual quad-core Xeon processor and 24 GB of RAM. The obtained results show better performance when compared with existing hardware and software implementations.

cs.CR↗

arXiv2020

Integrated Mobile Solutions in an Internet-of-Things Development Model

The Internet-of-Things (IoT) is a revolutionary technology that is rapidly changing the world. IoT systems strive to provide automated solutions for almost every life aspect; traditional devices are becoming connected, ubiquitous, pervasive, wireless, context-aware, smart, controlled through mobile solutions, to name but a few. IoT devices can now be found in our apartments, places of work, cars, buildings, and in almost every aspect of life. In this investigation, we propose an IoT system Development Model (IDM). The proposed IDM enables the development of IoT systems from concept to prototyping. The model comprises concept refinement pyramids, decision trees, realistic constraint lists, architecture and organization diagrams, communication interface patterns, use cases, and menus of analysis metrics and evaluation indicators. The investigation confirms that the proposed model enjoys several properties, such as, clarity, conciseness, thoroughness, productivity, etc. The model is deployed for a variety of systems that belong to heterogeneous areas of application; the model is proven to be effective in application and successful in integrating mobile solutions. This chapter includes the presentation of the IDM submodels, the reasoning about their usefulness, and the technical developments of several systems. The chapter includes thorough discussions, analysis of the model usability and application, and in-depth evaluations.

eess.SP↗

arXiv2019

Fuzzy Inference Procedure for Intelligent and Automated Control of Refrigerant Charging

Fuzzy logic controllers are readily customizable in natural language terms and can effectively deal with nonlinearities and uncertainties in control systems. This paper presents an intelligent and automated fuzzy control procedure for the refrigerant charging of refrigerators. The elements that affect the experimental charging and the optimization of the performance of refrigerators are fuzzified and used in an inference model. The objective is to represent the intelligent behavior of a human tester and ultimately make the developed model available for the use in an automated data acquisition, monitoring, and decision-making system. The proposed system is capable of determining the needed amount of refrigerant in the shortest possible time. The system automates the refrigerant charging and performance testing of parallel units. The system is built using data acquisition systems from National Instruments and programmed under LabVIEW. The developed fuzzy models, and their testing results, are evaluated according to their compatibility with the principles that govern the intelligent behavior of human experts when performing the refrigerant-charging process. In addition, comparisons of the fuzzy models with classical inference models are presented. The obtained results confirm that the proposed fuzzy controllers outperform traditional crisp controllers and provide major test time and energy savings. The paper includes thorough discussions, analysis, and evaluation.

eess.SP↗

arXiv2019

HTCC: Haskell to Handel-C Compiler

Functional programming languages, such as Haskell, enable simple, concise, and correct-by-construction hardware development. HTCC compiles a subset of Haskell to Handel-C language with hardware output. Moreover, HTCC generates VHDL, Verilog, EDIF, and SystemC programs. The design of HTCC compiler includes lexical, syntax and semantic analyzers. HTCC automates a transformational derivation methodology to rapidly produce hardware that maps onto Field Programmable Gate Arrays (FPGAs) . HTCC is generated using ANTLR compiler-compiler tool and supports an effective integrated development environment. This paper presents the design rationale and the implementation of HTCC. Several sample generations of first-class and higher-order functions are presented. In-addition, a compilation case-study is presented for the XTEA cipher. The investigation comprises a thorough evaluation and performance analysis. The targeted FPGAs include Cyclone II, Stratix IV, and Virtex-6 from Altera and Xilinx.

cs.PL↗

arXiv2019

A Unified Analysis Approach for Hardware and Software Implementations

Smart gadgets are being embedded almost in every aspect of our lives. From smart cities to smart watches, modern industries are increasingly supporting the Internet-of-Things (IoT). SysMART aims at making supermarkets smart, productive, and with a touch of modern lifestyle. While similar implementations to improve the shopping experience exists, they tend mainly to replace the shopping activity at the store with online shopping. Although online shopping reduces time and effort, it deprives customers from enjoying the experience. SysMART relies on cutting-edge devices and technology to simplify and reduce the time required during grocery shopping inside the supermarket. In addition, the system monitors and maintains perishable products in good condition suitable for human consumption. SysMART is built using state-of-the-art technologies that support rapid prototyping and precision data acquisition. The selected development environment is LabVIEW with its world-class interfacing libraries. The paper comprises a detailed system description, development strategy, interface design, software engineering, and a thorough analysis and evaluation.

cs.DC↗

arXiv2019

SysMART Outdoor Services: A System of Connected and Smart Supermarkets

Smart cities are today's modern trend. Many high-tech industrial firms are exploring different approaches to implement smart cities. Various projects aim at internet-of-things and smart solutions. Current implementations are mostly localized to a specific building or area; however, the growth is crossing space and geographic location limits. Shopping is a central activity that is frequent and typically a time-consuming task. SysMART is system of connected and smart supermarkets. SysMART enables a plausible shopping experience for customers. The aim of SysMART is to provide an advanced lifestyle with its ease of use functionality. SysMART outdoor services support distant parking availability, traffic status, and remote inventory checks for supermarkets in a chain. SysMART implementation relies on cutting edge technologies that support rapid prototyping and precision data acquisition, such as, National Instrument devices. The selected development environment is LabView with its world-class interfacing libraries. The paper comprises a detailed system description, development strategy, interface design, software engineering, and a thorough analysis and evaluation.

cs.OH↗

arXiv2019

SysMART Indoor Services: A System of Smart and Connected Supermarkets

Smart gadgets are being embedded almost in every aspect of our lives. From smart cities to smart watches, modern industries are increasingly supporting the Internet of Things (IoT). SysMART aims at making supermarkets smart, productive, and with a touch of modern lifestyle. While similar implementations to improve the shopping experience exists, they tend mainly to replace the shopping activity at the store with online shopping. Although online shopping reduces time and effort, it deprives customers from enjoying the experience. SysMART relies on cutting-edge devices and technology to simplify and reduce the time required during grocery shopping inside the supermarket. In addition, the system monitors and maintains perishable products in good condition suitable for human consumption. SysMART is built using state-of-the-art technologies that support rapid prototyping and precision data acquisition. The selected development environment is LabVIEW with its world-class interfacing libraries. The paper comprises a detailed system description, development strategy, interface design, software engineering, and a thorough analysis and evaluation.

eess.SP↗

arXiv2019

AmIE: An Ambient Intelligent Environment for Assisted Living

In the modern world of technology Internet-of-things (IoT) systems strives to provide an extensive interconnected and automated solutions for almost every life aspect. This paper proposes an IoT context-aware system to present an Ambient Intelligence (AmI) environment; such as an apartment, house, or a building; to assist blind, visually-impaired, and elderly people. The proposed system aims at providing an easy-to-utilize voice-controlled system to locate, navigate and assist users indoors. The main purpose of the system is to provide indoor positioning, assisted navigation, outside weather information, room temperature, people availability, phone calls and emergency evacuation when needed. The system enhances the user's awareness of the surrounding environment by feeding them with relevant information through a wearable device to assist them. In addition, the system is voice-controlled in both English and Arabic languages and the information are displayed as audio messages in both languages. The system design, implementation, and evaluation consider the constraints in common types of premises in Kuwait and in challenges, such as the training needed by the users. This paper presents cost-effective implementation options by the adoption of a Raspberry Pi microcomputer, Bluetooth Low Energy devices and an Android smart watch.

cs.CY↗

arXiv2019

Analysis of Pipelined KATAN Ciphers under Handle-C for FPGAs

Embedded Systems are everywhere from the smartphones we hold in our hands to the satellites that hover around the earth. These embedded systems are being increasingly integrated into our personal and commercial infrastructures. More than 98% of all processors are implanted and used in embedded systems rather than traditional computers. As a result, security in embedded systems now more than ever has become a major concern. Since embedded systems are designed to be low-cost, fast and real-time, it would be appropriate to use tiny, lightweight and highly secure cryptographic algorithms. KATAN and KATANTAN family of light-weight block ciphers are promising cryptographic options. In this paper, a sequential hardware design is developed under Handel-C. Taking a step further, Handel-C's parallel construct is taken advantage of to develop a parallel-pipelined hybrid implementation. Both sequential and parallel-pipelined implementations are tested under Altera Quartus to implement and analyze hardware designs in conjunction with DK Design Suite's Handel-C compiler. The developed designs are mapped to Altera's Stratix II that is one of the industry's highest bandwidth and density FPGAs. The results confirm that using Handel-C can provide faster implementations. The obtained results are promising and show better performance when compared with similar implementations-specifically the developed parallel-pipelined processor.

cs.DC↗

arXiv2019

Reconfigurable Hardware Implementation of the Successive Overrelaxation Method

In this chapter, we study the feasibility of implementing SOR in reconfigurable hardware. We use Handel-C, a higher level design tool, to code our design, which is analyzed, synthesized, and placed and routed using the FPGAs proprietary software (DK Design Suite, Xilinx ISE 8.1i, and Quartus II 5.1). We target Virtex II Pro, Altera Stratix, and Spartan3L, which is embedded in the RC10 FPGA-based system from Celoxica. We report our timing results when targeting Virtex II Pro and compare them to software version results written in C++ and running on a general purpose processor (GPP).

cs.DC↗

arXiv2019

Logic Design

Electronic circuits can be separated into two groups, digital and analog circuits. Analog circuits operate on analog quantities that are continuous in value, whereas digital circuits operate on digital quantities that are discrete in value and limited in precision. In practice, most digital systems contain combinational circuits along with memory; these systems are known as sequential circuits. Sequential circuits are of two types: synchronous and asynchronous. In a synchronous sequential circuit, a clock signal is used at discrete instants of time to synchronize desired operations. Asynchronous sequential circuits do not require synchronizing clock pulses; however, the completion of an operation signals the start of the next operation in sequence. The basic logic design steps are generally identical for sequential and combinational circuits; these are specification, formulation, optimization, and the implementation of the optimized equations using a suitable hardware technology. The differences between sequential and combinational design steps appear in the details of each step. The minimization (optimization) techniques used in logic design range from simple (manual) to complex (automated). An example of manual optimization methods is the Karnough map (K-map). Indeed, hardware implementation technology has been growing faster than the ability of designers to produce hardware designs. Hence, there has been a growing interest in developing techniques and tools that facilitate the process of logic design.

cs.OH↗

arXiv2019

Programmable Logic Arrays

Programmable logic arrays (PLAs) are traditional digital electronic devices. A PLA is a simple programmable logic device (SPLD) used to implement combinational logic circuits. A PLA has a set of programmable AND gates, which link to a set of programmable OR gates to produce an output. The AND-OR layout of a PLA allows for implementing logic functions that are in a sum-of-products form. PLAs are available in the market in different types. PLAs could be stand alone chips, or parts of bigger processing systems. Stand alone PLAs are available as mask programmable (MPLAs) and field programmable (FPLAs) devices. The attractions of PLAs that brought them to mainstream engineers include their simplicity, relatively small circuit area, predictable propagation delay, and ease of development. The powerful-but-simple property brought PLAs to rapid prototyping, synthesis, design optimization techniques, embedded systems, traditional computer systems, hybrid high-performance computing systems, etc. Indeed, there has been renewable interests in working with the simple AND-to-OR PLAs.

cs.OH↗

arXiv2019

2D and 3D Computer Graphics Algorithms under MorphoSys

This paper presents new mappings of 2D and 3D geometrical transformation on the MorphoSys (M1) reconfigurable computing (RC) prototype [2]. This improves the system performance as a graphics accelerator [1-5]. Three algorithms are mapped including two for calculating 2D transformations, and one for 3D transformations. The results presented indicate an improved performance. The speedup achieved is explained as well as the advantages in the mapping of the application. The transformations on an 8x8 RC array were run, and numerical examples were simulated to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operations. Comparisons with other systems are presented, namely, with Intel processing systems and Celoxica RC-1000 FPGA.

cs.DC↗

arXiv2019

High Performance Reconfigurable Computing Systems

The rapid progress and advancement in electronic chips technology provide a variety of new implementation options for system engineers. The choice varies between the flexible programs running on a general-purpose processor (GPP) and the fixed hardware implementation using an application specific integrated circuit (ASIC). Many other implementation options present, for instance, a system with a RISC processor and a DSP core. Other options include graphics processors and microcontrollers. Specialist processors certainly improve performance over general-purpose ones, but this comes as a quid pro quo for flexibility. Combining the flexibility of GPPs and the high performance of ASICs leads to the introduction of reconfigurable computing (RC) as a new implementation option with a balance between versatility and speed. The focus of this chapter is on introducing reconfigurable computers as modern super computing architectures. The chapter also investigates the main reasons behind the current advancement in the development of RC-systems. Furthermore, a technical survey of various RC-systems is included laying common grounds for comparisons. In addition, this chapter mainly presents case studies implemented under the MorphoSys RC-system. The selected case studies belong to different areas of application, such as, computer graphics and information coding. Parallel versions of the studied algorithms are developed to match the topologies supported by the MorphoSys. Performance evaluation and results analyses are included for implementations with different characteristics.

cs.AR↗

arXiv2019

Cyclic Coding Algorithms under MorphoSys Reconfigurable Computing System

This paper introduces reconfigurable computing (RC) and specifically chooses one of the prototypes in this field, MorphoSys (M1) [1 - 5]. The paper addresses the results obtained when using RC in mapping algorithms pertaining to digital coding in relation to previous research [6 - 10]. The chosen algorithms relate to cyclic coding techniques, namely the CCITT CRC-16 and the CRC-16. A performance analysis study of the M1 RC system is also presented to evaluate the efficiency of the algorithm execution on the M1 system. For comparison purposes, three other systems where used to map the same algorithms showing the advantages and disadvantages of each compared with the M1 system. The algorithms were run on the 8x8 RC (reconfigurable) array of the M1 (MorphoSys) system; numerical examples were simulated to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operations.

cs.IT↗

arXiv2019

Performance Analysis of Linear Algebraic Functions using Reconfigurable Computing

This paper introduces a new mapping of geometrical transformation on the MorphoSys (M1) reconfigurable computing (RC) system. New mapping techniques for some linear algebraic functions are recalled. A new mapping for geometrical transformation operations is introduced and their performance on the M1 system is evaluated. The translation and scaling transformation addressed in this mapping employ some vector-vector and vector-scalar operations [6-7]. A performance analysis study of the M1 RC system is also presented to evaluate the efficiency of the algorithm execution. Numerical examples were simulated to validate our results, using the MorphoSys mULATE program, which emulates M1 operations.

cs.AR↗

arXiv2019

Parallel Hardware for Faster Morphological Analysis

Morphological analysis in the Arabic language is computationally intensive, has numerous forms and rules, and is intrinsically parallel. The investigation presented in this paper confirms that the effective development of parallel algorithms and the derivation of corresponding processors in hardware enable implementations with appealing performance characteristics. The presented developments of parallel hardware comprise the application of a variety of algorithm modelling techniques, strategies for concurrent processing, and the creation of pioneering hardware implementations that target modern programmable devices. The investigation includes the creation of a linguistic-based stemmer for Arabic verb root extraction with extended infix processing to attain high-levels of accuracy. The implementations comprise three versions, namely, software, non-pipelined processor, and pipelined processor with high throughput. The targeted systems are high-performance multi-core processors for software implementations and high-end Field Programmable Gate Array systems for hardware implementations. The investigation includes a thorough evaluation of the methodology, and performance and accuracy analyses of the developed software and hardware implementations. The pipelined processor achieved a significant speedup of 5571.4 over the software implementation. The developed stemmer for verb root extraction with infix processing attained accuracies of 87% and 90.7% for analyzing the texts of the Holy Quran and its Chapter 29 - Surat Al-Ankabut.

cs.DC↗

arXiv2019

Optimizing FIR Filter Mapping on the Morphosys Reconfigurable System

This paper proposes an optimized mapping of the FIR filter algorithm that enhances the rate of a reconfigurable computer over a basic mapping previously proposed [1]. It also presents a new interconnection scheme in the reconfigurable part of MorphoSys, a reconfigurable computing system [2]. Reconfigurable computing (RC) is introduced, followed by the MorphoSys RC system. Two optimized FIR mappings are then presented which deliver enhanced speed. A spreadsheet model will detail the modification and the improvement. The speedup achieved is also explained as well as the advantages in the mapping of the application.

eess.SP↗