arXiv subjects

Jérémy Guichemerre

Publications and source records attributed to Jérémy Guichemerre.

6 recordsLinked to original sources

arXiv2026

An Open-Source Standard-Cell Library for IHP 130nm Developed by Students

Standard-cell libraries form the critical interface between transistor-level circuit design and automated digital design flows, yet their design and characterization are rarely covered in depth in digital VLSI courses. This paper presents VLSI 5, a graduate-level course at ETH Zurich in which students design, lay out, characterize, and integrate their own standard cells using IHP's open-source 130nm SG13G2 process design kit. In the first course offering, 19 students developed EZ130 8T, an open-source eight-track standard-cell library comprising 220 cells. We evaluate successive library versions using eight synthesis benchmarks, across which EZ130 8T achieves significant area reduction compared to the SG13G2 library at competitive timing. For a postlayout 8x8 matrix-vector multiplier, EZ130 8T reduces cell area by 35% and energy by 39% while maintaining virtually the same clock period. The library has already been adopted in other ETH Zurich VLSI courses, enabling the creation of chips entirely designed by students down to the transistor level.

cs.AR↗

arXiv2026

The Influence of Gain and Phase Mismatches on Beam Patterns in Phased Arrays

Practical implementations of phased arrays suffer from per-antenna gain, phase, and delay mismatches, which can significantly worsen the maximum sidelobe level (SLL) of beampatterns. The existing literature either analyzes specific structured mismatch patterns or derives per-angle marginal statistics under random mismatches, which fail to characterize global beampattern metrics such as the maximum SLL. To address this limitation, we propose a frequency-domain framework in which the beampattern is described by a tapering-window-dependent base function evaluated along a deformation determined by the array architecture and signal bandwidth. This formulation enables a spectral analysis of mismatches, revealing that element-wise errors generate weighted replicas of the ideal beampattern whose amplitudes are given by the discrete Fourier transform of the mismatch sequence. Building on this insight, we derive an approximation of the maximum SLL distribution under random gain and phase mismatches. The resulting expressions enable yield-oriented design and rapid design-space exploration without relying on computationally intensive Monte-Carlo simulations.

eess.SP↗

arXiv2026

Mitigating SAR-ADC Non-Idealities in Massive MU-MIMO Systems via Affine Models

Low-resolution data converters can significantly reduce the power consumption and silicon area of all-digital massive multi-user (MU) multiple-input multiple-output (MIMO) basestations. However, the existing literature almost exclusively focuses on idealistic quantization models, neglecting the inherent non-idealities present in real-world analog-to-digital converter (ADC) implementations. To overcome this limitation, we propose two affine models, one based on Bussgang's decomposition and one that maximizes the signal-to-distortion ratio (SDR), both accounting for the most prominent non-idealities in successive approximation register (SAR) ADCs. Subsequently, we utilize these models to devise low-complexity methods that mitigate SAR-ADC non-idealities in massive MU-MIMO wireless systems.

eess.SP↗

arXiv2026

Spectral Impact of Mismatches in Interleaved ADCs

Interleaved ADCs are critical for applications requiring multi-gigasample per second (GS/s) rates, but their performance is often limited by offset, gain, and timing skew mismatches across the sub-ADCs. We propose exact but compact expressions that describe the impact of each of those non-idealities on the output spectrum. We derive the distribution of the power of the induced spurs and replicas, critical for yield-oriented derivation of sub-ADC specifications. Finally, we provide a practical example in which calibration step sizes are derived under the constraint of a target production yield.

eess.SP↗

arXiv2025

A 14ns-Latency 9Gb/s 0.44mm$^2$ 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX

Ultra-reliable low latency communication (URLLC) is a key part of 5G wireless systems. Achieving low latency necessitates codes with short blocklengths for which polar codes with successive cancellation list (SCL) decoding typically outperform message-passing (MP)-based decoding of low-density parity-check (LDPC) codes. However, SCL decoders are known to exhibit high latency and poor area efficiency. In this paper, we propose a new short-blocklength multi-rate binary LDPC code that outperforms the 5G-LDPC code for the same blocklength and is suitable for URLLC applications using fully parallel MP. To demonstrate our code's efficacy, we present a 0.44mm$^2$ GlobalFoundries 22FDX LDPC decoder ASIC which supports three rates and achieves the lowest-in-class decoding latency of 14ns while reaching an information throughput of 9Gb/s at 62pJ/b energy efficiency for a rate-1/2 code with 128-bit blocklength.

cs.AR↗

arXiv2023

The Impact of SAR-ADC Mismatch on Quantized Massive MU-MIMO Systems

Low-resolution analog-to-digital converters (ADCs) in massive multi-user (MU) multiple-input multiple-output (MIMO) wireless systems can significantly reduce the power, cost, and interconnect data rates of infrastructure basestations. Thus, recent research on the theory and algorithm sides has extensively focused on such architectures, but with idealistic quantization models. However, real-world ADCs do not behave like ideal quantizers, and are affected by fabrication mismatches. We analyze the impact of capacitor-array mismatches in successive approximation register (SAR) ADCs, which are widely used in wireless systems. We use Bussgang's decomposition to model the effects of such mismatches, and we analyze their impact on the performance of a single ADC. We then simulate a massive MU-MIMO system to demonstrate that capacitor mismatches should not be ignored, even in basestations that use low-resolution SAR ADCs.

cs.IT↗