arXiv subjects

J. G. Gluschke

Publications and source records attributed to J. G. Gluschke.

11 recordsLinked to original sources

arXiv2026

Organic Electrochemical Transistor Arrays with Integrated Lipid-Sealed Femtolitre Chambers for Simultaneous Electrical and Optical Detection of Membrane Protein Activity

We report a scalable method for fabricating arrays of fifty-two ion-sensitive PEDOT:PSS organic electrochemical transistors (OECTs) on glass coverslips, each incorporating an integrated fluoropolymer microwell sealed with a lipid bilayer for simultaneous electrical and fluorescence microscopy studies of membrane proteins. The architecture addresses a key limitation of existing OECT arrays by providing every transistor with an independent fluid reservoir sealed by its own isolated segment of lipid bilayer, thereby confining membrane protein diffusion to a defined sensing region. Microwells containing a dye-labelled $50$~mM KCl solution were sealed with lipid bilayers and overlaid with a dye-free $100$~mM KCl solution. Following addition of $α$-hemolysin, formation of heptameric pores enabled K$^{+}$ ions to diffuse into the microwells and dye molecules to diffuse out, producing concurrent decreases in transistor conductance and fluorescence intensity. This integrated platform combines electrical and optical readout within independently addressable sensing sites and provides a versatile, scalable foundation for larger transistor arrays and the investigation of diverse membrane proteins reconstituted into lipid bilayers.

cond-mat.soft↗

arXiv2023

Post-growth shaping and transport anisotropy in 2D InAs nanofins

We report on the post-growth shaping of free-standing 2D InAs nanofins that are grown by selective-area epitaxy and mechanically transferred to a separate substrate for device fabrication. We use a citric acid based wet etch that enables complex shapes, e.g., van der Pauw cloverleaf structures, with patterning resolution down to 150 nm as well as partial thinning of the nanofin to improve the gate response. We exploit the high sensitivity of the cloverleaf structures to transport anisotropy to address the fundamental question of whether there is a measurable transport anisotropy arising from wurtzite/zincblende polytypism in 2D InAs nanostructures. We demonstrate a mobility anisotropy of order 2-4 at room temperature arising from polytypic stacking faults in our nanofins. Our work highlights a key materials consideration for devices featuring self-assembled 2D III-V nanostructures using advanced epitaxy methods.

cond-mat.mes-hall↗

arXiv2023

Integrated bioelectronic proton-gated logic elements utilizing nanoscale patterned Nafion

A central endeavour in bioelectronics is the development of logic elements to transduce and process ionic to electronic signals. Motivated by this challenge, we report fully monolithic, nanoscale logic elements featuring n- and p-type nanowires as electronic channels that are proton-gated by electron-beam patterned Nafion. We demonstrate inverter circuits with state-of-the-art ion-to-electron transduction performance giving DC gain exceeding 5 and frequency response up to 2 kHz. A key innovation facilitating the logic integration is a new electron-beam process for patterning Nafion with linewidths down to 125 nm. This process delivers feature sizes compatible with low voltage, fast switching elements. This expands the scope for Nafion as a versatile patternable high-proton-conductivity element for bioelectronics and other applications requiring nanoengineered protonic membranes and electrodes.

physics.app-ph↗

arXiv2020

Impact of invasive metal probes on Hall measurements in semiconductor nanostructures

Recent advances in bottom-up growth are giving rise to a range of new two-dimensional nanostructures. Hall effect measurements play an important role in their electrical characterization. However, size constraints can lead to device geometries that deviate significantly from the ideal of elongated Hall bars with currentless contacts. Many devices using these new materials have a low aspect ratio and feature metal Hall probes that overlap with the semiconductor channel. This can lead to a significant distortion of the current flow. We present experimental data from InAs 2D nanofin devices with different Hall probe geometries to study the influence of Hall probe length and width. We use finite-element simulations to further understand the implications of these aspects and expand the scope to contact resistance and sample aspect ratios. Our key finding is that invasive probes lead to a significant underestimation in the measured Hall voltage, typically of the order of 40-80%. This in turn leads to a subsequent proportional overestimation of carrier concentration and an underestimation of mobility

cond-mat.mes-hall↗

arXiv2019

A parylene coating system specifically designed for producing ultra-thin films for nanoscale device applications

We report on a parylene chemical vapor deposition system custom designed for producing ultra-thin parylene films (5-100 nm thickness) for use as an electrical insulator in nanoscale electronic devices, including as the gate insulator in transistors. The system features a small deposition chamber that can be isolated and purged for process termination, a quartz crystal microbalance for monitoring deposition, and a rotating angled stage to increase coating conformity. The system was mostly built from off-the-shelf vacuum fittings allowing for easy modification and reduced cost compared to commercial parylene coating systems. The production of ultra-thin parylene films for device applications is a niche not well catered to by commercial coating systems, which are typically designed to give thicker coatings (microns) with high uniformity over much larger areas. An added advantage of our design for nanoscale device applications is that the small deposition chamber is readily removable for transfer to a glovebox to enable parylene deposition onto pristine surfaces prepared in oxygen/water-free environments with minimal contamination.

cond-mat.mes-hall↗

arXiv2019

Regaining a spatial dimension: Mechanically transferrable two-dimensional InAs nanofins grown by selective area epitaxy

We report a method for growing rectangular InAs nanofins with deterministic length, width and height by dielectric-templated selective-area epitaxy. These freestanding nanofins can be transferred to lay flat on a separate substrate for device fabrication. A key goal was to regain a spatial dimension for device design compared to nanowires, whilst retaining the benefits of bottom-up epitaxial growth. The transferred nanofins were made into devices featuring multiple contacts for Hall effect and four-terminal resistance studies, as well as a global back-gate and nanoscale local top-gates for density control. Hall studies give a 3D electron density $2.5~-~5 \times 10^{17}$ cm$^{-3}$, corresponding to an approximate surface accumulation layer density $3~-~6 \times 10^{12}$ cm$^{-2}$ that agrees well with previous studies of InAs nanowires. We obtain Hall mobilities as high as $1200$ cm$^{2}$/Vs, field-effect mobilities as high as $4400$ cm$^{2}$/Vs and clear quantum interference structure at temperatures as high as $20$ K. Our devices show excellent prospects for fabrication into more complicated devices featuring multiple ohmic contacts, local gates and possibly other functional elements, e.g., patterned superconductor contacts, that may make them attractive options for future quantum information applications.

cond-mat.mes-hall↗

arXiv2018

Achieving short high-quality gate-all-around structures for horizontal nanowire field-effect transistors

We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique. Top gates were then defined aligned to the bottom gates to form gate-all-around structures. This approach overcomes significant limitations in minimal obtainable gate length and gate-length control in previous horizontal wrap-gated nanowire transistors that arise because the gate is defined by wet etching. In the method presented here gate-length control is limited by the resolution of the electron-beam-lithography process. We demonstrate the versatility of our approach by fabricating a device with an independent bottom gate, top gate, and gate-all-around structure as well as a device with three independent gate-all-around structures with 300 nm, 200 nm, and 150 nm gate length. Our method enables us to achieve sub-threshold swings as low as 38 mV/dec at 77 K for a 150 nm gate length.

physics.app-ph↗

arXiv2018

Using ultra-thin parylene films as an organic gate insulator in nanowire field-effect transistors

We report the development of nanowire field-effect transistors featuring an ultra-thin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally-coated nanowires, which we used to produce functional $Ω$-gate and gate-all-around structures. These give sub-threshold swings as low as 140 mV/dec and on/off ratios exceeding $10^3$ at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically-treated nanowire surfaces; a feature generally not possible with oxides produced by atomic layer deposition due to the surface `self-cleaning' effect. Our results highlight the potential for parylene as an alternative ultra-thin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

physics.app-ph↗

arXiv2018

p-GaAs nanowire MESFETs with near-thermal limit gating

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical sub-threshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio $\sim 10^{5}$, on-resistance ~700 k$Ω$, contact resistance ~30 k$Ω$, peak transconductance 1.2 $μ$S/$μ$m and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates whilst leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance.

cond-mat.mes-hall↗

arXiv2017

Towards low-dimensional hole systems in Be-doped GaAs nanowires

GaAs was central to the development of quantum devices but is rarely used for nanowire-based quantum devices with InAs, InSb and SiGe instead taking the leading role. p-type GaAs nanowires offer a path to studying strongly-confined 0D and 1D hole systems with strong spin-orbit effects, motivating our development of nanowire transistors featuring Be-doped p-type GaAs nanowires, AuBe alloy contacts and patterned local gate electrodes towards making nanowire-based quantum hole devices. We report on nanowire transistors with traditional substrate back-gates and EBL-defined metal/oxide top-gates produced using GaAs nanowires with three different Be-doping densities and various AuBe contact processing recipes. We show that contact annealing only brings small improvements for the moderately-doped devices under conditions of lower anneal temperature and short anneal time. We only obtain good transistor performance for moderate doping, with conduction freezing out at low temperature for lowly-doped nanowires and inability to reach a clear off-state under gating for the highly-doped nanowires. Our best devices give on-state conductivity 95 nS, off-state conductivity 2 pS, on-off ratio ~$10^{4}$, and sub-threshold slope 50 mV/dec at T = 4 K. Lastly, we made a device featuring a moderately-doped nanowire with annealed contacts and multiple top-gates. Top-gate sweeps show a plateau in the sub-threshold region that is reproducible in separate cool-downs and indicative of possible conductance quantization highlighting the potential for future quantum device studies in this material system.

cond-mat.mes-hall↗

arXiv2015

InAs nanowire transistors with multiple, independent wrap-gate segments

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favourable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.

cond-mat.mes-hall↗