arXiv subjects

James S. Clarke

Publications and source records attributed to James S. Clarke.

13 recordsLinked to original sources

arXiv2025

Operating two exchange-only qubits in parallel

Semiconductors are among the most promising platforms to implement large-scale quantum computers, as advanced manufacturing techniques allow fabrication of large quantum dot arrays. Various qubit encodings can be used to store and manipulate quantum information on these quantum dot arrays. Regardless of qubit encoding, precise control over the exchange interaction between electrons confined in quantum dots in the array is critical. Furthermore, it is necessary to execute high-fidelity quantum operations concurrently to make full use of the limited coherence of individual qubits. Here, we demonstrate the parallel operation of two exchange-only qubits, consisting of six quantum dots in a linear arrangement. Using randomized benchmarking techniques, we show that issuing pulses on the five barrier gates to modulate exchange interactions in a maximally parallel way maintains the quality of qubit control relative to sequential operation. The techniques developed to perform parallel exchange pulses can be readily adapted to other quantum-dot based encodings. Moreover, we show the first experimental demonstrations of an iSWAP gate and of a charge-locking Pauli spin blockade readout method. The results are validated using cross-entropy benchmarking, a technique useful for performance characterization of larger quantum computing systems; here it is used for the first time on a quantum system based on semiconductor technology.

quant-ph↗

arXiv2025

Short two-qubit pulse sequences for exchange-only spin qubits in 2D layouts

Exchange-only (EO) spin qubits in quantum dots offer an expansive design landscape for architecting scalable device layouts. The study of two-EO-qubit operations, which involve six electrons in six quantum dots, has so far been limited to a small number of the possible configurations, and previous works lack analyses of design considerations and implications for quantum error correction. Using a simple and fast optimization method, we generate complete pulse sequences for CX, CZ, iSWAP, leakage-controlled CX, and leakage-controlled CZ two-qubit gates on 450 unique planar six-dot topologies and analyze differences in sequence length (up to 43\% reduction) across topology classes. In addition, we show that relaxing constraints on post-operation spin locations can yield further reductions in sequence length; conversely, constraining these locations in a particular way generates a CXSWAP operation with minimal additional cost over a standard CX. We integrate this pulse library into the Intel quantum stack and experimentally verify pulse sequences on a Tunnel Falls chip for different operations in a linear-connectivity device to confirm that they work as expected. Finally, we explore architectural implications of these results for quantum error correction. Our work guides hardware and software design choices for future implementations of scalable quantum dot architectures.

quant-ph↗

arXiv2024

12-spin-qubit arrays fabricated on a 300 mm semiconductor manufacturing line

Intels efforts to build a practical quantum computer are focused on developing a scalable spin-qubit platform leveraging industrial high-volume semiconductor manufacturing expertise and 300 mm fabrication infrastructure. Here, we provide an overview of the design, fabrication, and demonstration of a new customized quantum test chip, which contains 12-quantum-dot spin-qubit linear arrays, code named Tunnel Falls. These devices are fabricated using immersion and extreme ultraviolet lithography (EUV), along with other standard high-volume manufacturing (HVM) processes, as well as production-level process control. We present key device features and fabrication details, as well as qubit characterization results confirming device functionality. These results corroborate our fabrication methods and are a crucial step towards scaling of extensible 2D qubit array schemes.

cond-mat.mes-hall↗

arXiv2024

Probing single electrons across 300 mm spin qubit wafers

Building a fault-tolerant quantum computer will require vast numbers of physical qubits. For qubit technologies based on solid state electronic devices, integrating millions of qubits in a single processor will require device fabrication to reach a scale comparable to that of the modern CMOS industry. Equally importantly, the scale of cryogenic device testing must keep pace to enable efficient device screening and to improve statistical metrics like qubit yield and voltage variation. Spin qubits based on electrons in Si have shown impressive control fidelities but have historically been challenged by yield and process variation. Here we present a testing process using a cryogenic 300 mm wafer prober to collect high-volume data on the performance of hundreds of industry-manufactured spin qubit devices at 1.6 K. This testing method provides fast feedback to enable optimization of the CMOS-compatible fabrication process, leading to high yield and low process variation. Using this system, we automate measurements of the operating point of spin qubits and probe the transitions of single electrons across full wafers. We analyze the random variation in single-electron operating voltages and find that the optimized fabrication process leads to low levels of disorder at the 300 mm scale. Together these results demonstrate the advances that can be achieved through the application of CMOS industry techniques to the fabrication and measurement of spin qubit devices.

quant-ph↗

arXiv2022

Spiderweb array: A sparse spin-qubit array

One of the main bottlenecks in the pursuit of a large-scale--chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture that integrates on-chip control electronics, allowing for a significant reduction in the number of signal connections at the chip boundary. By arranging the qubits in a two-dimensional (2D) array with $\sim$12 $μ$m pitch, we create space to implement locally integrated sample-and-hold circuits. This allows to offset the inhomogeneities in the potential landscape across the array and to globally share the majority of the control signals for qubit operations. We make use of advanced circuit modeling software to go beyond conceptual drawings of the component layout, to assess the feasibility of the scheme through a concrete floor plan, including estimates of footprints for quantum and classical electronics, as well as routing of signal lines across the chip using different interconnect layers. We make use of local demultiplexing circuits to achieve an efficient signal-connection scaling leading to a Rent's exponent as low as $p = 0.43$. Furthermore, we use available data from state-of-the-art spin qubit and microelectronics technology development, as well as circuit models and simulations, to estimate the operation frequencies and power consumption of a million-qubit processor. This work presents a novel and complementary approach to previously proposed architectures, focusing on a feasible scheme to integrating quantum and classical hardware, and significantly closing the gap towards a fully CMOS-compatible quantum computer implementation.

quant-ph↗

arXiv2020

Effect of quantum Hall edge strips on valley splitting in silicon quantum wells

We determine the energy splitting of the conduction-band valleys in two-dimensional electrons confined to low-disorder Si quantum wells. We probe the valley splitting dependence on both perpendicular magnetic field $B$ and Hall density by performing activation energy measurements in the quantum Hall regime over a large range of filling factors. The mobility gap of the valley-split levels increases linearly with $B$ and is strikingly independent of Hall density. The data are consistent with a transport model in which valley splitting depends on the incremental changes in density $eB/h$ across quantum Hall edge strips, rather than the bulk density. Based on these results, we estimate that the valley splitting increases with density at a rate of 116 $μ$eV/10$^{11}$cm$^{-2}$, consistent with theoretical predictions for near-perfect quantum well top interfaces.

cond-mat.mes-hall↗

arXiv2020

Enhancing a Near-Term Quantum Accelerator's Instruction Set Architecture for Materials Science Applications

Quantum computers with tens to hundreds of noisy qubits are being developed today. To be useful for real-world applications, we believe that these near-term systems cannot simply be scaled-down non-error-corrected versions of future fault-tolerant large-scale quantum computers. These near-term systems require specific architecture and design attributes to realize their full potential. To efficiently execute an algorithm, the quantum coprocessor must be designed to scale with respect to qubit number and to maximize useful computation within the qubits' decoherence bounds. In this work, we employ an application-system-qubit co-design methodology to architect a near-term quantum coprocessor. To support algorithms from the real-world application area of simulating the quantum dynamics of a material system, we design a (parameterized) arbitrary single-qubit rotation instruction and a two-qubit entangling controlled-Z instruction. We introduce dynamic gate set and paging mechanisms to implement the instructions. To evaluate the functionality and performance of these two instructions, we implement a two-qubit version of an algorithm to study a disorder-induced metal-insulator transition and run 60 random instances of it, each of which realizes one disorder configuration and contains 40 two-qubit instructions (or gates) and 104 single-qubit instructions. We observe the expected quantum dynamics of the time-evolution of this system.

quant-ph↗

arXiv2019

A sparse spin qubit array with integrated control electronics

Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.

quant-ph↗

arXiv2018

Impact of qubit connectivity on quantum algorithm performance

Quantum computing hardware is undergoing rapid development from proof-of-principle devices to scalable machines that could eventually challenge classical supercomputers on specific tasks. On platforms with local connectivity, the transition from one- to two-dimensional arrays of qubits is seen as a natural technological step to increase the density of computing power and to reduce the routing cost of limited connectivity. Here we map and schedule representative algorithmic workloads - the Quantum Fourier Transform (QFT) relevant to factoring, the Grover diffusion operator relevant to quantum search, and Jordan-Wigner parity rotations relevant to simulations of quantum chemistry and materials science - to qubit arrays with varying connectivity. In particular we investigate the impact of restricting the ideal all-to-all connectivity to a square grid, a ladder and a linear array of qubits. Our schedule for the QFT on a ladder results in running time close to that of a system with all-to-all connectivity. Our results suggest that some common quantum algorithm primitives can be optimized to have execution times on systems with limited connectivities, such as a ladder and linear array, that are competitive with systems that have all-to-all connectivity

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arXiv2018

The critical role of substrate disorder in valley splitting in Si quantum wells

Motivated by theoretical predictions that spatially complex concentration modulations of Si and Ge can increase the valley splitting in quantum wells, we grow and characterize Si/SiGe heterostructures with a thin, pure Ge layer at the top of the quantum well using chemical vapor deposition. We show that these heterostructures remain hosts for high-mobility electron gases. We measure two quantum wells with approximately five monolayers of pure Ge at the upper barrier, finding mobilities as high as 70,000 cm$^2$/Vs, compared to 100,000 cm$^2$/Vs measured in samples with no Ge layer. Activation energy measurements in quantum Hall states corresponding to Fermi levels in the gap between different valley states reveal energy gaps ranging from 30 to over 200 $μ$eV, and we extract a surprisingly strong dependence of the energy gap on electron density. We interpret our results using tight binding theory and argue that our results are evidence that atomic scale disorder at the quantum well interface dominates the behavior of the valley splittings of these modified heterostructures.

cond-mat.mes-hall↗

arXiv2018

Rent's rule and extensibility in quantum computing

Quantum computing is on the verge of a transition from fundamental research to practical applications. Yet, to make the step to large-scale quantum computation, an extensible qubit system has to be developed. In classical semiconductor technology, this was made possible by the invention of the integrated circuit, which allowed to interconnect large numbers of components without having to solder to each and every one of them. Similarly, we expect that the scaling of interconnections and control lines with the number of qubits will be a central bottleneck in creating large-scale quantum technology. Here, we define the quantum Rent's exponent $p$ to quantify the progress in overcoming this challenge at different levels throughout the quantum computing stack. We further discuss the concept of quantum extensibility as an indicator of a platform's potential to reach the large quantum volume needed for universal quantum computing and review extensibility limits faced by different qubit implementations on the way towards truly large-scale qubit systems.

quant-ph↗

arXiv2016

Effect of strain, thickness, and local surface environment on electron transport properties of oxygen-terminated copper thin films

Electron transport is studied in surface oxidized single-crystal copper thin films with a thickness of up to 5.6 nm by applying density functional theory and density functional tight binding methods to determine electron transport properties within the ballistic regime. The variation of the electron transmission as a function of film thickness as well as the different contributions to the overall electron transmission as a function of depth into the the films is examined. Transmission at the oxidized copper film surfaces is found to be universally low. Films with thickness greater than 2.7 nm exhibit a similar behavior in local transmission per unit area with depth from the film surface; transmission per unit area initially increases rapidly and then plateaus at a depth of approximately 0.35-0.5 nm away from the surface, dependent on surface facet. Unstrained films tend to exhibit a higher transmission per unit area than corresponding films under tensile strain.

cond-mat.mes-hall↗

arXiv2016

Electron transport properties of sub-3-nm diameter copper nanowires

Density functional theory and density functional tight-binding are applied to model electron transport in copper nanowires of approximately 1 nm and 3 nm diameters with varying crystal orientation and surface termination. The copper nanowires studied are found to be metallic irrespective of diameter, crystal orientation and/or surface termination. Electron transmission is highly dependent on crystal orientation and surface termination. Nanowires oriented along the [110] crystallographic axis consistently exhibit the highest electron transmission while surface oxidized nanowires show significantly reduced electron transmission compared to unterminated nanowires. Transmission per unit area is calculated in each case, for a given crystal orientation we find that this value decreases with diameter for unterminated nanowires but is largely unaffected by diameter in surface oxidized nanowires for the size regime considered. Transmission pathway plots show that transmission is larger at the surface of unterminated nanowires than inside the nanowire and that transmission at the nanowire surface is significantly reduced by surface oxidation. Finally, we present a simple model which explains the transport per unit area dependence on diameter based on transmission pathways results.

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