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James S. Plank

Publications and source records attributed to James S. Plank.

13 recordsLinked to original sources
arXiv2026

A Spatiotemporal Extension of the Neuromorphic DBSCAN Implementation

DBSCAN is an algorithm that denoises and clusters data. In prior work, we implemented the DBSCAN algorithm neuromorphically, introducing two constructions termed ``flat'' and ``systolic''. The ``flat'' construction prioritizes throughput, while the ``systolic'' construction trades time for space resulting in a smaller, more hardware-friendly architecture at the cost of throughput. In this work, we offer spatiotemporal extensions of these two constructions to better leverage the spatiotemporal nature of event sensor data. Moreover, as in our prior work, we discuss partial or segmented implementations that further leverage time for space when hardware resources are constrained. All network constructions are provided as open-source implementations.

cs.NE↗
arXiv2024

A Neuromorphic Implementation of the DBSCAN Algorithm

DBSCAN is an algorithm that performs clustering in the presence of noise. In this paper, we provide two constructions that allow DBSCAN to be implemented neuromorphically, using spiking neural networks. The first construction is termed "flat," resulting in large spiking neural networks that compute the algorithm quickly, in five timesteps. Moreover, the networks allow pipelining, so that a new DBSCAN calculation may be performed every timestep. The second construction is termed "systolic", and generates much smaller networks, but requires the inputs to be spiked in over several timesteps, column by column. We provide precise specifications of the constructions and analyze them in practical neuromorphic computing settings. We also provide an open-source implementation.

cs.NE↗
arXiv2023

Optimizations for a Current-Controlled Memristor-based Neuromorphic Synapse Design

The synapse is a key element of neuromorphic computing in terms of efficiency and accuracy. In this paper, an optimized current-controlled memristive synapse circuit is proposed. Our proposed synapse demonstrates reliability in the face of process variation and the inherent stochastic behavior of memristors. Up to an 82% energy optimization can be seen during the SET operation over prior work. In addition, the READ process shows up to 54% energy savings. Our current-controlled approach also provides more reliable programming over traditional programming methods. This design is demonstrated with a 4-bit memory precision configuration. Using a spiking neural network (SNN), a neuromorphic application analysis was performed with this precision configuration. Our optimized design showed up to 82% improvement in control applications and a 2.7x improvement in classification applications compared with other design cases.

cs.ET↗
arXiv2023

Functional Specification of the RAVENS Neuroprocessor

RAVENS is a neuroprocessor that has been developed by the TENNLab research group at the University of Tennessee. Its main focus has been as a vehicle for chip design with memristive elements; however it has also been the vehicle for all-digital CMOS development, plus it has implementations on FPGA's, microcontrollers and software simulation. The software simulation is supported by the TENNLab neuromorphic software framework so that researchers may develop RAVENS solutions for a variety of neuromorphic computing applications. This document provides a functional specification of RAVENS that should apply to all implementations of the RAVENS neuroprocessor.

cs.NE↗
arXiv2022

Disclosure of a Neuromorphic Starter Kit

This paper presents a Neuromorphic Starter Kit, which has been designed to help a variety of research groups perform research, exploration and real-world demonstrations of brain-based, neuromorphic processors and hardware environments. A prototype kit has been built and tested. We explain the motivation behind the kit, its design and composition, and a prototype physical demonstration.

cs.NE↗
arXiv2022

The Case for RISP: A Reduced Instruction Spiking Processor

In this paper, we introduce RISP, a reduced instruction spiking processor. While most spiking neuroprocessors are based on the brain, or notions from the brain, we present the case for a spiking processor that simplifies rather than complicates. As such, it features discrete integration cycles, configurable leak, and little else. We present the computing model of RISP and highlight the benefits of its simplicity. We demonstrate how it aids in developing hand built neural networks for simple computational tasks, detail how it may be employed to simplify neural networks built with more complicated machine learning techniques, and demonstrate how it performs similarly to other spiking neurprocessors.

cs.NE↗
arXiv2021

An Oracle and Observations for the OpenAI Gym / ALE Freeway Environment

The OpenAI Gym project contains hundreds of control problems whose goal is to provide a testbed for reinforcement learning algorithms. One such problem is Freeway-ram-v0, where the observations presented to the agent are 128 bytes of RAM. While the goals of the project are for non-expert AI agents to solve the control problems with general training, in this work, we seek to learn more about the problem, so that we can better evaluate solutions. In particular, we develop on oracle to play the game, so that we may have baselines for success. We present details of the oracle, plus optimal game-playing situations that can be used for training and testing AI agents.

cs.AI↗
arXiv2020

User Manual CAI version-1.0: An Open-Source Toolbox for Computer-Aided Investigation on the Fundamental Limits of Information Systems

We provide an open source toolbox on https://github.com/ct2641/CAI/releases/tag/1.0 to conduct computer-aided investigation on the fundamental limits of information systems. The toolbox relies on either Gurobi or Cplex as the linear program solving engine. The program can read a problem description file, and then fulfill the following tasks: 1) compute a bound for a given linear combination of information measures and provide the value of information measures at the optimal solution; 2) efficiently compute a polytope tradeoff outer bound between two information quantities; 3) produce a proof (as a weighted sum of known information inequalities; and 4) provide the range for information quantities between which the optimal value does not change (sensitivity analysis). This technical report provides an overview of this toolbox, a detailed description of the syntax of the problem description file, and a few example use cases.

cs.IT↗
arXiv2019

Stochasticity and Robustness in Spiking Neural Networks

Artificial neural networks normally require precise weights to operate, despite their origins in biological systems, which can be highly variable and noisy. When implementing artificial networks which utilize analog 'synaptic' devices to encode weights, however, inherent limits are placed on the accuracy and precision with which these values can be encoded. In this work, we investigate the effects that inaccurate synapses have on spiking neurons and spiking neural networks. Starting with a mathematical analysis of integrate-and-fire (IF) neurons, including different non-idealities (such as leakage and channel noise), we demonstrate that noise can be used to make the behavior of IF neurons more robust to synaptic inaccuracy. We then train spiking networks which utilize IF neurons with and without noise and leakage, and experimentally confirm that the noisy networks are more robust. Lastly, we show that a noisy network can tolerate the inaccuracy expected when hafnium-oxide based resistive random-access memory is used to encode synaptic weights.

cs.NE↗
arXiv2017

A Survey of Neuromorphic Computing and Neural Networks in Hardware

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture. This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems. The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities. In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history. We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications. We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled. The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed.

cs.NE↗
arXiv2014

Construction of Partial MDS (PMDS) and Sector-Disk (SD) Codes with Two Global Parity Symbols

Partial MDS (PMDS) codes are erasure codes combining local (row) correction with global additional correction of entries, while Sector-Disk (SD) codes are erasure codes that address the mixed failure mode of current RAID systems. It has been an open problem to construct general codes that have the PMDS and the SD properties, and previous work has relied on Monte-Carlo searches. In this paper, we present a general construction that addresses the case of any number of failed disks and in addition, two erased sectors. The construction requires a modest field size. This result generalizes previous constructions extending RAID~5 and RAID~6.

cs.IT↗
arXiv2013

Construction of two SD Codes

SD codes are erasure codes that address the mixed failure mode of current RAID systems. Rather than dedicate entire disks to erasure coding, as done in RAID-5, RAID-6 and Reed-Solomon coding, an SD code dedicates entire disks, plus individual sectors to erasure coding. The code then tolerates combinations of disk and sector errors, rather than solely disk errors. It is been an open problem to construct general codes that have the SD property, and previous work has relied on Monte Carlo searches. In this paper, we present two general constructions that address the cases with one disk and two sectors, and two disks and two sectors. Additionally, we make an observation about shortening SD codes that allows us to prune Monte Carlo searches.

cs.IT↗