arXiv subjects

James T. Meech

Publications and source records attributed to James T. Meech.

6 recordsLinked to original sources

arXiv2024

Electron-Tunnelling-Noise Programmable Random Variate Accelerator for Monte Carlo Sampling

This article presents an electron tunneling noise programmable random variate accelerator for accelerating the sampling stage of Monte Carlo simulations. We used the LiteX framework to generate a FemtoRV imfc RISC-V instruction set soft processor and deploy it on a Digilent Arty-100T FPGA development board. The RISC-V soft processor augmented with our programmable random variate accelerator achieves an average speedup of 8.70 times and a median speedup of 8.68 times for a suite of twelve different benchmark applications when compared to GNU Scientific Library software random number generation. These speedups are achievable because the benchmarks spend an average of 90.0 % of their execution time generating random samples. The results of the Monte Carlo benchmark programs run over the programmable random variate accelerator have an average Wasserstein distance of 1.48 times and a median Wasserstein distance of 1.41 times that of the results produced by the GNU Scientific Library random number generators. The soft processor samples the electron tunneling noise source using the hardened XADC block in the FPGA. The flexibility of the LiteX framework allows for the deployment of any LiteX-supported soft processor with an electron tunneling noise programmable random variate accelerator on any LiteX-supported development board that contains an FPGA with an XADC.

cs.AR↗

arXiv2023

The Data Conversion Bottleneck in Analog Computing Accelerators

Most modern computing tasks have digital electronic input and output data. Due to these constraints imposed by real-world use cases of computer systems, any analog computing accelerator, whether analog electronic or optical, must perform an analog-to-digital conversion on its input data and a subsequent digital-to-analog conversion on its output data. The energy and latency costs incurred by data conversion place performance limits on analog computing accelerators. To avoid this overhead, analog hardware must replace the full functionality of traditional digital electronic computer hardware. This is not currently possible for optical computing accelerators due to limitations in gain, input-output isolation, and information storage in optical hardware. This article presents a case study that profiles 27 benchmarks for an analog optical Fourier transform and convolution accelerator which we designed and built. The case study shows that an ideal optical Fourier transform and convolution accelerator can produce an average speedup of 9.4 times and a median speedup of 1.9 times for the set of benchmarks. The optical Fourier transform and convolution accelerator only produces significant speedup for pure Fourier transform (45.3 times) and convolution (159.4 times) applications.

cs.AR↗

arXiv2023

Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design

We present a new high-level synthesis methodology for using large language model tools to generate hardware designs. The methodology uses exclusively open-source tools excluding the large language model. As a case study, we use our methodology to generate a permuted congruential random number generator design with a wishbone interface. We verify the functionality and quality of the random number generator design using large language model-generated simulations and the Dieharder randomness test suite. We document all the large language model chat logs, Python scripts, Verilog scripts, and simulation results used in the case study. We believe that our method of hardware design generation coupled with the open source silicon 130 nm design tools will revolutionize application-specific integrated circuit design. Our methodology significantly lowers the bar to entry when building domain-specific computing accelerators for the Internet of Things and proof of concept prototypes for later fabrication in more modern process nodes.

cs.AR↗

arXiv2023

Is This Computing Accelerator Evaluation Full of Hot Air?

Computing accelerators must significantly improve at least one metric such as: cost, speed, or efficiency for customers to find them useful. They must do this for at least one application that large numbers of users care about to become a commercial success. Furthermore, accelerators must improve the metric that customers care most about for a given application. We show that it is trivial to build an embedded sensor system that improves temperature sampling speed by 38,142 times and energy efficiency by 2 times compared to the state of the art in an application where these metrics do not matter. We then explain that this computing accelerator is not likely to displace the bimetallic kettle switch in the market because consumers are optimizing for cost, not temperature measurement sampling speed and efficiency when they buy a kettle.

cs.AR↗

arXiv2021

An Algorithm for Sensor Data Uncertainty Quantification

This article presents an algorithm for reducing measurement uncertainty of one physical quantity when given oversampled measurements of two physical quantities with correlated noise. The algorithm assumes that the aleatoric measurement uncertainty in both physical quantities follows a Gaussian distribution and relies on sampling faster than it is possible for the measurand (the true value of the physical quantity that we are trying to measure) to change (due to the system thermal time constant) to calculate the parameters of the noise distribution. In contrast to the Kalman and particle filters, which respectively require state update equations and a map of one physical quality, our algorithm requires only the oversampled sensor measurements. When applied to temperature-compensated humidity sensors, it provides reduced uncertainty in humidity estimates from correlated temperature and humidity measurements. In an experimental evaluation, the algorithm achieves average uncertainty reduction of 10.3 %. The algorithm incurs an execution time overhead of 5.3 % when compared to the minimum algorithm required to measure and calculate the uncertainty. Detailed instruction-level emulation of a C-language implementation compiled to the RISC-V architecture shows that the uncertainty reduction program required 0.05 % more instructions per iteration than the minimum operations required to calculate the uncertainty.

eess.SP↗

arXiv2021

Machine Learning for Sensor Transducer Conversion Routines

Sensors with digital outputs require software conversion routines to transform the unitless analogue-to-digital converter samples to physical quantities with correct units. These conversion routines are computationally complex given the limited computational resources of low-power embedded systems. This article presents a set of machine learning methods to learn new, less-complex conversion routines that do not sacrifice accuracy for the BME680 environmental sensor. We present a Pareto analysis of the tradeoff between accuracy and computational overhead for the models and models that reduce the computational overhead of the existing industry-standard conversion routines for temperature, pressure, and humidity by 62%, 71 %, and 18 % respectively. The corresponding RMS errors are 0.0114 degrees C, 0.0280 KPa, and 0.0337 %. These results show that machine learning methods for learning conversion routines can produce conversion routines with reduced computational overhead which maintain good accuracy.

cs.LG↗