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Jan Borovsky

Publications and source records attributed to Jan Borovsky.

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20 Second Parity Lifetime in an InAs--Pb Tetron Device

A central promise of topological quantum computing is that increasing the excitation gap improves device performance significantly. Here, we experimentally validate this principle in an InAs--Pb tetron device via interferometric single-shot parity measurements. By replacing aluminum with the higher-gap superconductor lead in our superconductor-semiconductor hybrid devices, we have improved the robustness of our topological phase. In addition, to enable fast and precise bring-up at scale, we have developed an rf measurement technique that resolves low-energy wire-end states and directly measures their energy splitting with $\mu\text{eV}$ precision. We employ this technique to bring up a device in a multi-tetron array and perform parity measurements of one of the tetron's hybrid nanowires (NWs). By controllably switching the wire parity, we observe $h/2e$-periodic bimodal shifts in the quantum capacitance of a quantum dot coupled to the hybrid nanowire in an interference loop. Further time-resolved measurements reveal a characteristic parity switching time of $\sim 20$ s with some instances reaching minute-scale. Such extremely long parity lifetimes are orders of magnitude longer than typical qubit operation times, which are on the order of $\mu\text{s}$. Finally, we discuss potential implications for the fidelity of Pauli measurements.

cond-mat.mes-hall

Distinct Lifetimes for $X$ and $Z$ Loop Measurements in a Majorana Tetron Device

We present a hardware realization and measurements of a tetron qubit device in a superconductor-semiconductor heterostructure. The device architecture contains two parallel superconducting nanowires, which support four Majorana zero modes (MZMs) when tuned into the topological phase, and a trivial superconducting backbone. Two distinct readout interferometers are formed by connecting the superconducting structure to a series of quantum dots. We perform single-shot interferometric measurements of the fermion parity for the two loops, designed to implement Pauli-$X$ and $Z$ measurements of the tetron. Performing repeated single-shot measurements yields two widely separated time scales $\tau_X = 14.5\pm 0.3 \, \mathrm{\mu s}$ and $\tau_Z = 12.4\pm 0.4\, \mathrm{ms}$ for parity switches observed in the $X$ and $Z$ measurement loops, which we attribute to intra-wire parity switches and external quasiparticle poisoning, respectively. We estimate assignment errors of $\mathrm{err}^X_a=16\%$ and $\mathrm{err}^Z_a=0.5\%$ for $X$ and $Z$ measurement-based operations, respectively.

cond-mat.mes-hall

Roadmap to fault tolerant quantum computation using topological qubit arrays

We describe a concrete device roadmap towards a fault-tolerant quantum computing architecture based on noise-resilient, topologically protected Majorana-based qubits. Our roadmap encompasses four generations of devices: a single-qubit device that enables a measurement-based qubit benchmarking protocol; a two-qubit device that uses measurement-based braiding to perform single-qubit Clifford operations; an eight-qubit device that can be used to show an improvement of a two-qubit operation when performed on logical qubits rather than directly on physical qubits; and a topological qubit array supporting lattice surgery demonstrations on two logical qubits. Devices that enable this path require a superconductor-semiconductor heterostructure that supports a topological phase, quantum dots and coupling between those quantum dots that can create the appropriate loops for interferometric measurements, and a microwave readout system that can perform fast, low-error single-shot measurements. We describe the key design components of these qubit devices, along with the associated protocols for demonstrations of single-qubit benchmarking, Clifford gate execution, quantum error detection, and quantum error correction, which differ greatly from those in more conventional qubits. Finally, we comment on implications and advantages of this architecture for utility-scale quantum computation.

quant-ph