arXiv subjects

Jason D. Chadwick

Publications and source records attributed to Jason D. Chadwick.

9 recordsLinked to original sources

arXiv2026

CAbLECAR: efficiently scheduling QLDPC codes on a tileable spin qubit chip with shuttling

Semiconductor spin qubits are a promising platform for large-scale quantum computing, but have yet to take full advantage of the broad class of quantum low-density parity check (QLDPC) codes, which promise high encoding rates and efficient logic but require nonlocal connectivity between physical qubits. In this work, we investigate the implementation of QLDPC codes on a tileable, shuttling-based spin qubit architecture. By tailoring syndrome extraction circuits to the shuttling noise model, we significantly improve on previous surface code proposals and extend the feasible shuttling range of the architecture by 5-10x, enabling the implementation of more complex codes with long-range interactions. Taking inspiration from the field of robotics, we develop a coordinated shuttle scheduling algorithm that supports arbitrary codes and use it to benchmark the logical performance of a variety of promising code families. We find that the optimized schedules are up to 86% faster than hand-optimized schedules for certain code families. Through detailed circuit-level simulations, we identify specific QLDPC codes that improve upon prior surface code implementations by orders of magnitude, increasing encoding efficiency and reducing logical error rates. This work demonstrates the potential of shuttling-based spin qubit hardware platforms for scalable and efficient fault-tolerant quantum computation.

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arXiv2025

A manufacturable surface code architecture for spin qubits with fast transversal logic

Spin qubits in silicon quantum dot arrays are a promising quantum computation platform for long-term scalability due to their small qubit footprint and compatibility with advanced semiconductor manufacturing. However, spin qubit devices face a key architectural bottleneck: the large physical footprint of readout components relative to qubits prevents a dense layout where all qubits can be measured simultaneously, complicating the implementation of quantum error correction. This challenge is offset by the platform's unique rapid shuttling capability, which can be used to transport qubits to distant readout ports. In this work, we explore the design constraints and capabilities of spin qubits in silicon and propose the SNAQ (Shuttling-capable Narrow Array of spin Qubits) surface code architecture, which relaxes the 1:1 readout-to-qubit assumption by leveraging spin shuttling to time-multiplex ancilla qubit initialization and readout. Our analysis shows that, given sufficiently high (experimentally demonstrated) qubit coherence times, SNAQ delivers an orders-of-magnitude reduction in chip area per logical qubit. Additionally, by using a denser grid of physical qubits, SNAQ enables fast transversal logic for short-distance logical operations, achieving over 10x improvement in local logical clock speed while still supporting global operations via lattice surgery. This translates to a 3.2-5.7x improvement in key Adder and Lookup fault-tolerant subroutines. Our work pinpoints critical hardware metrics and provides a compelling path toward high-performance fault-tolerant computation on near-term-manufacturable spin qubit arrays.

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arXiv2025

Erasure Minesweeper: exploring hybrid-erasure surface code architectures for efficient quantum error correction

Dual-rail erasure qubits can substantially improve the efficiency of quantum error correction, allowing lower error rates to be achieved with fewer qubits, but each erasure qubit requires $3\times$ more transmons to implement compared to standard qubits. In this work, we introduce a hybrid-erasure architecture for surface code error correction where a carefully chosen subset of qubits is designated as erasure qubits while the rest remain standard. Through code-capacity analysis and circuit-level simulations, we show that a hybrid-erasure architecture can boost the performance of the surface code -- much like how a game of Minesweeper becomes easier once a few squares are revealed -- while using fewer resources than a full-erasure architecture. We study strategies for the allocation and placement of erasure qubits through analysis and simulations. We then use the hybrid-erasure architecture to explore the trade-offs between per-qubit cost and key logical performance metrics such as threshold and effective distance in surface code error correction. Our results show that the strategic introduction of dual-rail erasure qubits in a transmon architecture can enhance the logical performance of surface codes for a fixed transmon budget, particularly for near-term-relevant transmon counts and logical error rates.

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arXiv2025

Operating two exchange-only qubits in parallel

Semiconductors are among the most promising platforms to implement large-scale quantum computers, as advanced manufacturing techniques allow fabrication of large quantum dot arrays. Various qubit encodings can be used to store and manipulate quantum information on these quantum dot arrays. Regardless of qubit encoding, precise control over the exchange interaction between electrons confined in quantum dots in the array is critical. Furthermore, it is necessary to execute high-fidelity quantum operations concurrently to make full use of the limited coherence of individual qubits. Here, we demonstrate the parallel operation of two exchange-only qubits, consisting of six quantum dots in a linear arrangement. Using randomized benchmarking techniques, we show that issuing pulses on the five barrier gates to modulate exchange interactions in a maximally parallel way maintains the quality of qubit control relative to sequential operation. The techniques developed to perform parallel exchange pulses can be readily adapted to other quantum-dot based encodings. Moreover, we show the first experimental demonstrations of an iSWAP gate and of a charge-locking Pauli spin blockade readout method. The results are validated using cross-entropy benchmarking, a technique useful for performance characterization of larger quantum computing systems; here it is used for the first time on a quantum system based on semiconductor technology.

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arXiv2024

Short two-qubit pulse sequences for exchange-only spin qubits in 2D layouts

Exchange-only (EO) spin qubits in quantum dots offer an expansive design landscape for architecting scalable device layouts. The study of two-EO-qubit operations, which involve six electrons in six quantum dots, has so far been limited to a small number of the possible configurations, and previous works lack analyses of design considerations and implications for quantum error correction. Using a simple and fast optimization method, we generate complete pulse sequences for CX, CZ, iSWAP, leakage-controlled CX, and leakage-controlled CZ two-qubit gates on 450 unique planar six-dot topologies and analyze differences in sequence length (up to 43\% reduction) across topology classes. In addition, we show that relaxing constraints on post-operation spin locations can yield further reductions in sequence length; conversely, constraining these locations in a particular way generates a CXSWAP operation with minimal additional cost over a standard CX. We integrate this pulse library into the Intel quantum stack and experimentally verify pulse sequences on a Tunnel Falls chip for different operations in a linear-connectivity device to confirm that they work as expected. Finally, we explore architectural implications of these results for quantum error correction. Our work guides hardware and software design choices for future implementations of scalable quantum dot architectures.

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arXiv2024

Predictive Window Decoding for Fault-Tolerant Quantum Programs

Real-time decoding is a key ingredient in future fault-tolerant quantum systems, yet many decoders are too slow to run in real time. Prior work has shown that parallel window decoding schemes can scalably meet throughput requirements in the presence of increasing decoding times, given enough classical resources. However, windowed decoding schemes require that some decoding tasks be delayed until others have completed, which can be problematic during time-sensitive operations such as T gate teleportation, leading to suboptimal program runtimes. To alleviate this, we introduce a speculative window decoding scheme. Taking inspiration from branch prediction in classical computer architecture our decoder utilizes a light-weight speculation step to predict data dependencies between adjacent decoding windows, allowing multiple layers of decoding tasks to be resolved simultaneously. Through a state-of-the-art compilation pipeline and a detailed simulator, we find that speculation reduces application runtimes by 40% on average compared to prior parallel window decoders.

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arXiv2024

Averting multi-qubit burst errors in surface code magic state factories

Fault-tolerant quantum computation relies on the assumption of time-invariant, sufficiently low physical error rates. However, current superconducting quantum computers suffer from frequent disruptive noise events, including cosmic ray impacts and shifting two-level system defects. Several methods have been proposed to mitigate these issues in software, but they add large overheads in terms of physical qubit count, as it is difficult to preserve logical information through burst error events. We focus on mitigating multi-qubit burst errors in magic state factories, which are expected to comprise up to 95% of the space cost of future quantum programs. Our key insight is that magic state factories do not need to preserve logical information over time; once we detect an increase in local physical error rates, we can simply turn off parts of the factory that are affected, re-map the factory to the new chip geometry, and continue operating. This is much more efficient than previous more general methods, and is resilient even under many simultaneous impact events. Using precise physical noise models, we show an efficient ray detection method and evaluate our strategy in different noise regimes. Compared to existing baselines, we find reductions in ray-induced overheads by several orders of magnitude, reducing total qubitcycle cost by geomean 6.5x to 13.9x depending on the noise model. This work reduces the burden on hardware by providing low-overhead software mitigation of these errors.

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arXiv2024

Dancing the Quantum Waltz: Compiling Three-Qubit Gates on Four Level Architectures

Superconducting quantum devices are a leading technology for quantum computation, but they suffer from several challenges. Gate errors, coherence errors and a lack of connectivity all contribute to low fidelity results. In particular, connectivity restrictions enforce a gate set that requires three-qubit gates to be decomposed into one- or two-qubit gates. This substantially increases the number of two-qubit gates that need to be executed. However, many quantum devices have access to higher energy levels. We can expand the qubit abstraction of $|0\rangle$ and $|1\rangle$ to a ququart which has access to the $|2\rangle$ and $|3\rangle$ state, but with shorter coherence times. This allows for two qubits to be encoded in one ququart, enabling increased virtual connectivity between physical units from two adjacent qubits to four fully connected qubits. This connectivity scheme allows us to more efficiently execute three-qubit gates natively between two physical devices. We present direct-to-pulse implementations of several three-qubit gates, synthesized via optimal control, for compilation of three-qubit gates onto a superconducting-based architecture with access to four-level devices with the first experimental demonstration of four-level ququart gates designed through optimal control. We demonstrate strategies that temporarily use higher level states to perform Toffoli gates and always use higher level states to improve fidelities for quantum circuits. We find that these methods improve expected fidelities with increases of 2x across circuit sizes using intermediate encoding, and increases of 3x for fully-encoded ququart compilation.

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arXiv2023

Efficient control pulses for continuous quantum gate families through coordinated re-optimization

We present a general method to quickly generate high-fidelity control pulses for any continuously-parameterized set of quantum gates after calibrating a small number of reference pulses. We find that interpolating between optimized control pulses for different quantum operations does not immediately yield a high-fidelity intermediate operation. To solve this problem, we propose a method to optimize control pulses specifically to provide good interpolations. We pick several reference operations in the gate family of interest and optimize pulses that implement these operations, then iteratively re-optimize the pulses to guide their shapes to be similar for operations that are closely related. Once this set of reference pulses is calibrated, we can use a straightforward linear interpolation method to instantly obtain high-fidelity pulses for arbitrary gates in the continuous operation space. We demonstrate this procedure on the three-parameter Cartan decomposition of two-qubit gates to obtain control pulses for any arbitrary two-qubit gate (up to single-qubit operations) with consistently high fidelity. Compared to previous neural network approaches, the method is 7.7x more computationally efficient to calibrate the pulse space for the set of all single-qubit gates. Our technique generalizes to any number of gate parameters and could easily be used with advanced pulse optimization algorithms to allow for better translation from simulation to experiment.

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