arXiv subjects

Javad Javidan

Publications and source records attributed to Javad Javidan.

5 recordsLinked to original sources

arXiv2023

Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m)

Finite field multiplier is mainly used in error-correcting codes and signal processing. Finite field multiplier is regarded as the bottleneck arithmetic unit for such applications and it is the most complicated operation over finite field GF(2m) which requires a huge amount of logic resources. In this paper, a new modified serial-in parallel-out multiplication algorithm with interleaved modular reduction is suggested. The proposed method offers efficient area architecture as compared to proposed algorithms in the literature. The reduced finite field multiplier complexity is achieved by means of utilizing logic NAND gate in a particular architecture. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency, critical path) and space (gate-latch number) complexity. A detailed comparative analysis indicates that, the proposed finite field multiplier based on logic NAND gate outperforms previously known results

cs.IT↗

arXiv2023

High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF(2m)

The utilization of finite field multipliers is pervasive in contemporary digital systems, with hardware implementation for bit parallel operation often necessitating millions of logic gates. However, various digital design issues, whether inherent or stemming from soft errors, can result in gate malfunction, ultimately can cause gates to malfunction, which in turn results in incorrect multiplier outputs. Thus, to prevent susceptibility to error, it is imperative to employ a reliable finite field multiplier implementation that boasts a robust fault detection capability. In order to achieve the best fault detection performance for finite field detection performance for finite field multipliers while maintaining a low-complexity implementation, this study proposes a novel fault detection scheme for a recent bit-parallel polynomial basis over GF(2m). The primary concept behind the proposed approach is centered on the implementation of an efficient BCH decoder that utilize Berlekamp-Rumsey-Solomon (BRS) algorithm and Chien-search method to effectively locate errors with minimal delay. The results of our synthesis indicate that our proposed error detection and correction architecture for a 45-bit multiplier with 5-bit errors achieves a 37% and 49% reduction in critical path delay compared to existing designs. Furthermore, a 45-bit multiplicand with five errors has hardware complexity that is only 80%, which is significantly less complex than the most advanced BCH-based fault recognition techniques, such as TMR, Hamming's single error correction, and LDPC-based methods for finite field multiplication which is desirable in constrained applications, such as smart cards, IoT devices, and implantable medical devices.

cs.IT↗

arXiv2023

Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes

The size reduction of transistors in the latest flash memory generation has resulted in programming and data erasure issues within these designs. Consequently, ensuring reliable data storage has become a significant challenge for these memory structures. To tackle this challenge, error-correcting codes like BCH (Bose-Chaudhuri-Hocquenghem) codes are employed in the controllers of these memories. When decoding BCH codes, two crucial factors are the delay in error correction and the hardware requirements of each sub-block. This article proposes an effective solution to enhance error correction speed and optimize the decoder circuit's efficiency. It suggests implementing a parallel architecture for the BCH decoder's sub-blocks and utilizing pipeline techniques. Moreover, to reduce the hardware requirements of the BCH decoder block, an algorithm based on XOR sharing is introduced to eliminate redundant gates in the search Chien block. The proposed decoder is simulated using the VHDL hardware description language and subsequently synthesized with Xilinx ISE software. Simulation results indicate that the proposed algorithm not only significantly reduces error correction time but also achieves a noticeable reduction in the hardware overhead of the BCH decoder block compared to similar methods.

cs.IT↗

arXiv2023

Efficient Fault Detection Architecture of Bit-Parallel Multiplier in Polynomial Basis of GF(2m) Using BCH Code

The finite field multiplier is mainly used in many of today's state of the art digital systems and its hardware implementation for bit parallel operation may require millions of logic gates. Natural causes or soft errors in digital design could cause some of these gates to malfunction in the field, which could cause the multiplier to produce incorrect outputs. To ensure that they are not susceptible to error, it is crucial to use a finite field multiplier implementation that is effective and has a high fault detection capability. In this paper, we propose a novel fault detection scheme for a recent bit-parallel polynomial basis multiplier over GF(2m), where the proposed method aims at obtaining high fault detection performance for finite field multipliers and meanwhile maintain low-complexity implementation which is favored in resource constrained applications such as smart cards. The proposed method is based on BCH error correction codes, with an area-delay efficient architecture. The experimental results show that for 45-bit multiplier with 5-bit errors the proposed error detection and correction architecture results in 37% and %49 reduction in critical path delay with compared to the existing method in [18]. Moreover, the area overhead for 45-bit multiplier with 5 errors is within 80% which is significantly lower than the best existing BCH based fault detection method in finite field multiplier [18].

cs.IT↗

arXiv2022

An Efficient Digital Watermarking Algorithm Based on DCT and BCH Error Correcting Code

Watermarking is a technique for hiding of data in a medium coverage so that its presence is not detectable by a human eye and is recoverable only by the authorized recipient. Two of the most important features of watermarked image are transparency and robustness which are largely related to the security of watermarking algorithms. In this paper, an image watermarking scheme based on BCH error correction code in Discrete Cosine Transformation (DCT) domain is considered. Before embedding process, the watermark is encoded through BCH coding. Then it is embedded into the Discrete Cosine Transformation (DCT) coefficients of cover image. In order to decrease embedding complexity and speed up the process of finding the best position to insert a watermark signal, lookup table method is utilized. The key features of proposed method include the reduction of time required in the process embedding of information, security and ability to correct the error caused by variety of attacks and destructions as well. Watermarked image robustness has been investigated against different kinds attacks and the simulation results indicate that the proposed algorithm outperforms the existing methods in terms of imperceptibility, robustness and security.

cs.MM↗