arXiv subjects

Javed I. Khan

Publications and source records attributed to Javed I. Khan.

8 recordsLinked to original sources

arXiv2026

Ethical Risk Assessment of the Data Harnessing Process of LLM supported on Consensus of Well-known Multi-Ethical Frameworks

The rapid advancements in large language models (LLMs) have revolutionized natural language processing, unlocking unprecedented capabilities in communication, automation, and knowledge generation. However, the ethical implications of LLM development, particularly in data harnessing, remain a critical challenge. Despite widespread discussion about the ethical compliance of LLMs -- especially concerning their data harnessing processes, there remains a notable absence of concrete frameworks to systematically guide or measure the ethical risks involved. In this paper we discuss a potential pathway for building an Ethical Risk Scoring (ERS) system to quantitatively assess the ethical integrity of the data harnessing process for AI systems. This system is based on a set of assessment questions grounded in core ethical principles, which are, in turn, supported by commanding ethical theories. By integrating measurable scoring mechanisms, this approach aims to foster responsible LLM development, balancing technological innovation with ethical accountability.

cs.CY↗

arXiv2026

In Quest of an Extensible Multi-Level Harm Taxonomy for Adversarial AI: Heart of Security, Ethical Risk Scoring and Resilience Analytics

Harm is invoked everywhere from cybersecurity, ethics, risk analysis, to adversarial AI, yet there exists no systematic or agreed upon list of harms, and the concept itself is rarely defined with the precision required for serious analysis. Current discourse relies on vague, under specified notions of harm, rendering nuanced, structured, and qualitative assessment effectively impossible. This paper challenges that gap directly. We introduce a structured and expandable taxonomy of harms, grounded in an ensemble of contemporary ethical theories, that makes harm explicit, enumerable, and analytically tractable. The proposed framework identifies 66+ distinct harm types, systematically organized into two overarching domains human and nonhuman, and eleven major categories, each explicitly aligned with eleven dominant ethical theories. While extensible by design, the upper levels are intentionally stable. Beyond classification, we introduce a theory-aware taxonomy of victim entities and formalize normative harm attributes, including reversibility and duration that materially alter ethical severity. Together, these contributions transform harm from a rhetorical placeholder into an operational object of analysis, enabling rigorous ethical reasoning and long term safety evaluation of AI systems and other sociotechnical domains where harm is a first order concern.

cs.CY↗

arXiv2023

ZePoP: A Distributed Leader Election Protocol using the Delay-based Closeness Centrality for Peer-to-Peer Applications

This paper presents ZePoP, a leader election protocol for distributed systems, optimizing a delay-based closeness centrality. We design the protocol specifically for the Peer to Peer(P2P) applications, where the leader peer (node) is responsible for collecting, processing, and redistributing data or control signals satisfying some timing constraints. The protocol elects an optimal leader node in the dynamically changing network and constructs a Data Collection and Distribution Tree (DCDT) rooted at the leader node. The elected optimal leader is closest to all nodes in the system compared to other nodes. We validate the proposed protocol through theoretical proofs as well as experimental results.

cs.DC↗

arXiv2022

Preprint: Open Source Compiling for V1Model RMT Switch: Making Data Center Networking Innovation Accessible

Very few of the innovations in deep networking have seen data center scale implementation. Because the Data Center network's extreme scale performance requires hardware implementation, which is only accessible to a few. However, the emergence of reconfigurable match-action table (RMT) paradigm-based switches have finally opened up the development life cycle of data plane devices. The P4 language is the dominant language choice for programming these devices. Now, Network operators can implement the desired feature over white box RMT switches. The process involves an innovator writing new algorithms in the P4 language and getting them compiled for the target hardware. However, there is still a roadblock. After designing an algorithm, the P4 program's compilation technology is not fully open-source. Thus, it is very difficult for an average researcher to get deep insight into the performance of his/her innovation when executed at the silicon level. There is no open-source compiler backend available for this purpose. Proprietary compiler backends provided by different hardware vendors are available for this purpose. However, they are closed-source and do not provide access to the internal mapping mechanisms. Which inhibits experimenting with new mapping algorithms and innovative instruction sets for reconfigurable match-action table architecture. This paper describes our work toward an open-source compiler backend for compiling P416 targeted for the V1Model architecture-based programmable switches.

cs.NI↗

arXiv2022

An Open-Source P416 Compiler Backend for Reconfigurable Match-Action Table Switches

The P4 language has become the dominant choice for programming the reconfigurable match-action table based programmable switches. V1Model architecture is the most widely available realization of this paradigm. The open-source compiler frontend developed by the P4 consortium can execute syntax analysis and derive a hardware-independent representation of a program written using the latest version of P4 (also known as P416 ). A compiler backend is required to map this intermediate representation to the hardware resources of a V1Model switch. However, there is no open-source compiler backend available to check the realizability of a P416 program over a V1Model switch. Proprietary tools provided by different hardware vendors are available for this purpose. However, they are closed source and do not provide access to the internal mapping mechanisms. Which inhibits experimenting with new mapping algorithms and innovative instruction sets for reconfigurable match-action table architecture. Moreover, the proprietary compiler backends are costly and come with various non-disclosure agreements. These factors pose serious challenges to programmable switch-related research. In this work, we present an open-source P416 compiler backend for the V1Model architecture-based programmable switches. It uses heuristic-based mapping algorithms to map a P416 program over the hardware resources of a V1Model switch. It allows developers to rapidly prototype different mapping algorithms. It also gives various resource usage statistics of a P416 program, enabling comparison among multiple P416 schemes.

cs.NI↗

arXiv2022

P4TE: PISA Switch Based Traffic Engineering in Fat-Tree Data Center Networks

This work presents P4TE, an in-band traffic monitoring, load-aware packet forwarding, and flow rate controlling mechanism for traffic engineering in fat-tree topology-based data center networks using PISA switches. It achieves sub-RTT reaction time to change in network conditions, improved flow completion time, and balanced link utilization. Unlike the classical probe-based monitoring approach, P4TE uses an in-band monitoring approach to identify traffic events in the data plane. Based on these events, it re-adjusts the priorities of the paths. It uses a heuristic-based load-aware forwarding path selection mechanism to respond to changing network conditions and control the flow rate by sending feedback to the end hosts. It is implementable on emerging v1model.p4 architecture-based programmable switches and capable of maintaining the line-rate performance. Our evaluation shows that P4TE uses a small amount of resources in the PISA pipeline and achieves an improved flow completion time than ECMP and HULA.

cs.NI↗

arXiv2021

Identifying and Modeling Security Threats for IoMT Edge Network using Markov Chain and Common Vulnerability Scoring System (CVSS)

In this work, we defined an attack vector for networks utilizing the Internet of Medical Things (IoMT) devices and compute the probability distribution of IoMT security threats based on Markov chain and Common Vulnerability Scoring System (CVSS). IoMT is an emerging technology that improves patients' quality of life by permitting personalized e-health services without restrictions on time and site. The IoMT consists of embedded objects, sensors, and actuators that transmit and receive medical data. These Medical devices are vulnerable to different types of security threats, and thus, they pose a significant risk to patient's privacy and safety. Because security is a critical factor for successfully merging IoMT into pervasive healthcare systems, there is an urgent need for new security mechanisms to prevent threats on the IoMT edge network. Toward this direction, the first step is defining an attack vector that an attacker or unauthorized user can take advantage of to penetrate and tamper with medical data. In this article, we specify a threat model for the IoMT edge network. We identify any vulnerabilities or weaknesses within the IoMT network that allow unauthorized privileges and threats that can utilize these weaknesses to compromise the IoMT edge network. Finally, we compute the probability distribution of IoMT threats based on the Markov transition probability matrix.

cs.CR↗

arXiv2020

Toward an Abstract Model of Programmable Data Plane Devices

SDN divides the networking landscape into 2 parts: control and data plane. SDN expanded it's foot mark starting with OpenFlow based highly flexible control plane and rigid data plane. Innovation and improvement in hardware design and development is bringing various new architectures for data plane. Data plane is becoming more programmable then ever before. A common abstract model of data plane is required to develop complex application over these heterogeneous data plane devices. It can also provide insight about performance optimization and bench-marking of programmable data plane devices. Moreover, to understand and utilize data plane's programmability, a detailed structural analysis and an identifiable matrix to compare different devices are required. In this work, an improved and structured abstract model of the programmable data plane devices is presented and features of its components are discussed in detail. Several commercially available programmable data plane devices are also compared based on those features.

cs.NI↗