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Jeremie Pope

Publications and source records attributed to Jeremie Pope.

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Profiling the Effective Limits of Error Mitigation via Circuit Replication

Current era quantum computers continue to grow in both capability and capacity. Despite these advancements, errors induced by environmental noise severely limit practical applicability. Current research into error mitigation and correction to bridge the gap between current-era quantum computers and the execution of noise-sensitive workloads. These methods have significant performance and resource overheads, thereby greatly limiting the real-world benefits of their use. Circuit replication, as a naive form of error mitigation, is not new and has largely been ignored given the resource constraints of current quantum hardware. However, its simplicity is attractive as a means to supplement modern methods, reducing the overall performance overhead while still preserving error-mitigation capabilities. In this paper, we profile the effects of simple circuit replication under real-world noise profiles to better establish replication's limits as a supplemental mitigation strategy. Quantum Approximate Optimization Algorithm (QAOA) for the Maxcut problem is explored for the analysis. For small graphs, we found that the average inference strength decreases by approximately 21.8% while the average standard deviation decreases by 108.8% compared to 6 replicates. For larger graphs, inference strength decreases by 35.4% while the average standard deviation decreased only 20.5%. Fewer replications did not affect smaller graphs, but degraded inference strength, with comparable benefits to standard deviation in larger graphs. These results show that replication has potential uses as a supplemental mitigation strategy for large-depth, highly variable workloads.

quant-ph

Not All Qubits are Utilized Equally

Improvements to the functionality of modern Noisy Intermediate-Scale Quantum (NISQ) computers have coincided with an increase in the total number of physical qubits. Quantum programmers do not commonly design circuits that directly utilize these qubits; instead, they rely on various software suites to algorithmically transpile the circuit into one compatible with a target machine's architecture. For connectivity-constrained superconducting architectures in particular, the chosen syntheses, layout, and routing algorithms used to transpile a circuit drastically change the average utilization patterns of physical qubits. In this paper, we analyze average qubit utilization of a quantum hardware as a means to identify how various transpiler configurations change utilization patterns. We present the preliminary results of this analysis using IBM's 27-qubit Falcon R4 architecture on the Qiskit platform for a subset of qubits, gate distributions, and optimization configurations. We found a persistent bias towards trivial mapping, which can be addressed through increased optimization provided that the overall utilization of an architecture remains below a certain threshold. As a result, some qubits are overused whereas other remain underused. The implication of our study are many-fold namely, (a) potential reduction in calibration overhead by focusing on overused qubits, (b) refining optimization, mapping and routing algorithms to maximize the hardware utilization and (c) pricing underused qubits at low rate to motivate their usage and improve hardware throughput (applicable in multi-tenant environments).

quant-ph