arXiv subjects

Jerry Zhao

Publications and source records attributed to Jerry Zhao.

4 recordsLinked to original sources

arXiv2026

Dynamics of Null and Electrostatic Blind Spots for Quantitative PFM

Piezoresponse force microscopy is a cornerstone technique for probing nanoscale electromechanical phenomena, yet quantitative and in some cases qualitative interpretation remains hindered by parasitic electrostatic forces coupled through cantilever dynamics. Recent approaches aim to suppress these artifacts by operating at resonance defined null spots or electrostatic blind spots, but whether these conditions are equivalent and how they evolve under realistic measurement conditions has remained unclear. Here, combining analytical beam models, geometrically faithful finite-element simulations, and automated interferometric measurements, we show that NS and ESBS are fundamentally different operating conditions. The NS is a modal zero at contact resonance where sensitivity to all excitations vanishes, whereas the ESBS is a quasistatic position where only the distributed electrostatic response is suppressed. Automated measurements reveal that both conditions evolve with the tip sample boundary condition yet remain spatially separated under realistic experimental conditions. While beam models capture the dominant cantilever mechanics, finite-element simulations and experiment show that quantitative prediction of near tip behavior requires realistic three dimensional probe electrostatics and mechanics. These findings establish NS and ESBS as dynamic operating conditions and provide a practical framework for advancing interferometric PFM toward truly quantitative electromechanical metrology.

cond-mat.mtrl-sci↗

arXiv2024

Instruction Scheduling in the Saturn Vector Unit

While the challenges and solutions for efficient execution of scalable vector ISAs on long-vector-length microarchitectures have been well established, not all of these solutions are suitable for short-vector-length implementations. This work proposes a novel microarchitecture for instruction sequencing in vector units with short architectural vector lengths. The proposed microarchitecture supports fine-granularity chaining, multi-issue out-of-order execution, zero dead-time, and run-ahead memory accesses with low area or complexity costs. We present the Saturn Vector Unit, a RTL implementation of a RVV vector unit. With our instruction scheduling mechanism, Saturn exhibits comparable or superior power, performance, and area characteristics compared to state-of-the-art long-vector and short-vector implementations.

cs.AR↗

arXiv2022

Efficient and Accurate Quantized Image Super-Resolution on Mobile NPUs, Mobile AI & AIM 2022 challenge: Report

Image super-resolution is a common task on mobile and IoT devices, where one often needs to upscale and enhance low-resolution images and video frames. While numerous solutions have been proposed for this problem in the past, they are usually not compatible with low-power mobile NPUs having many computational and memory constraints. In this Mobile AI challenge, we address this problem and propose the participants to design an efficient quantized image super-resolution solution that can demonstrate a real-time performance on mobile NPUs. The participants were provided with the DIV2K dataset and trained INT8 models to do a high-quality 3X image upscaling. The runtime of all models was evaluated on the Synaptics VS680 Smart Home board with a dedicated edge NPU capable of accelerating quantized neural networks. All proposed solutions are fully compatible with the above NPU, demonstrating an up to 60 FPS rate when reconstructing Full HD resolution images. A detailed description of all models developed in the challenge is provided in this paper.

eess.IV↗

arXiv2021

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration

DNN accelerators are often developed and evaluated in isolation without considering the cross-stack, system-level effects in real-world environments. This makes it difficult to appreciate the impact of System-on-Chip (SoC) resource contention, OS overheads, and programming-stack inefficiencies on overall performance/energy-efficiency. To address this challenge, we present Gemmini, an open-source*, full-stack DNN accelerator generator. Gemmini generates a wide design-space of efficient ASIC accelerators from a flexible architectural template, together with flexible programming stacks and full SoCs with shared resources that capture system-level effects. Gemmini-generated accelerators have also been fabricated, delivering up to three orders-of-magnitude speedups over high-performance CPUs on various DNN benchmarks. * https://github.com/ucb-bar/gemmini

cs.DC↗