arXiv subjects

Jian-Yu Lin

Publications and source records attributed to Jian-Yu Lin.

4 recordsLinked to original sources

arXiv2026

Size-Dependent Band-Tail Localization in Oxide Semiconductors Revealed by Direct Density-of-States Mapping

Disorder-induced localization is expected to become increasingly important as amorphous oxide semiconductor transistors are scaled toward low-dimensional channels, yet the electronic states responsible for this transport regime remain difficult to resolve experimentally. Here, we use a lock-in-based electric-field penetration technique to directly map the effective density of states (DOS) in In-based oxide semiconductor thin-film transistors (TFTs). The extracted quantum capacitance, carrier density, and chemical potential reveal a disorder-dominated transport regime in which band-tail states are not merely passive traps, but become screening-active and partially transport-active. Geometry-dependent DOS mapping shows an exponential suppression of the effective DOS with channel length, demonstrating size-dependent band-tail localization and providing a microscopic origin for a distinct localization-induced threshold-voltage roll-off mechanism. Temperature-dependent measurements show that the disorder-dominated DOS is strongly suppressed at low temperatures, while extended diffusive states remain nearly unchanged, confirming the localization origin. By tuning film thickness, O2 annealing, and In/Ga/Zn composition, we further demonstrate systematic suppression of disorder and effective-DOS localization. This work establishes direct DOS mapping as a device-level probe of localization physics and provides a pathway for engineering disorder in low-dimensional oxide semiconductor electronics.

cond-mat.mes-hall↗

arXiv2026

200 mm Wafer-Scale Monolithic 3D Integration of Atomic Layer-Deposited Oxide Semiconductors

Monolithic 3D (M3D) integration offers a pathway to overcome the scaling limits of conventional silicon complementary metal-oxide-semiconductor (CMOS) technology by extending dense vertical stacking of multifunctional logic and memory devices. Here, we demonstrate wafer-scale M3D integration of three tiers of atomic-layer-deposited (ALD) indium oxide (InOx)-based devices (>100,000 fabricated), including ferroelectric, enhancement-mode, and depletion-mode field-effect transistors, on 200 mm silicon wafers. We achieve threshold voltage standard deviation as low as 0.04 V, average electron mobility up to 91.6 cm2V-1s-1, and fully functional cross-tier circuits. A four-tier 3D computing-in-memory (CIM) accelerator targeting large language model workloads is developed using a custom InOx process design kit, delivering 1.4x to 2.9x speedup and comparable energy-delay product improvements over 2D baselines. These results establish ALD InOx M3D integration as a scalable and CMOS-compatible platform for next-generation artificial intelligence hardware and advanced electronics.

physics.app-ph↗

arXiv2026

Breakdown of Ohm's Law by Disorders in Low-Dimensional Transistors

Ohm's law provides a fundamental framework for understanding charge transport in conductors and underpins the concept of electrical scaling that has enabled the continuous advancement of modern CMOS technologies. As transistors are scaled to even smaller dimensions, device channels inevitably enter low-dimensional regimes to achieve higher performance. Low-dimensional materials such as atomically thin oxide semiconductors, 2D van der Waals semiconductors, and 1D carbon nanotubes, have thus emerged as key candidates for extending Moore's law. Here, we reveal the fundamental distinction between three-dimensional and low-dimensional conductors arising from disorder-induced electron localization, which leads to the breakdown of Ohm's law and lateral linear scaling. We develop a quantitative model that captures the role of the disordered region, a unique characteristic intrinsically to low-dimensional transistors. Furthermore, the disorder-induced localization framework consistently explains experimental observations in atomically thin In2O3 field-effect transistors across variations in channel length, temperature, thickness, and post-annealing conditions. This work establishes a unified physical picture for understanding and optimizing disorder-driven electronic transport in low-dimensional transistors.

cond-mat.mes-hall↗

arXiv2024

Ultralow Voltage Operation of p- and n-FETs Enabled by Self-Formed Gate Dielectric and Metal Contacts on 2D Tellurium

The ongoing demand for more energy-efficient, high-performance electronics is driving the exploration of innovative materials and device architectures, where interfaces play a crucial role due to the continuous downscaling of device dimensions. Tellurium (Te), in its two-dimensional (2D) form, offers significant potential due to its high carrier mobility and ambipolar characteristics, with the carrier type easily tunable via surface modulation. In this study, we leverage atomically controlled material transformations in 2D Te to create intimate junctions, enabling near-ideal field-effect transistors (FETs) for both n-type and p-type operation. A NiTex-Te contact provides highly transparent interfaces, resulting in low contact resistance, while the TiOx-Te gate dielectric forms an ultraclean interface with a capacitance equivalent to 0.88 nm equivalent oxide thickness (EOT), where the quantum capacitance of Te is observed. Subthreshold slopes (SS) approach the Boltzmann limit, with a record-low SS of 3.5 mV/dec achieved at 10 K. Furthermore, we demonstrate 2D Te-based complementary metal-oxide-semiconductor (CMOS) inverters operating at an ultralow voltage of 0.08 V with a voltage gain of 7.1 V/V. This work presents a promising approach to forming intimate dielectric/semiconductor and metal/semiconductor junctions for next-generation low-power electronic devices.

physics.app-ph↗