arXiv subjects

Jiayuan Shen

Publications and source records attributed to Jiayuan Shen.

10 recordsLinked to original sources

arXiv2026

Proving olympiad geometry theorems on a superconducting quantum processor

Automated theorem proving seeks to use computational systems to prove or disprove mathematical and logical statements [1, 2]. It underpins a wide range of applications, and enhancing theorem-proving capabilities remains a central objective in artificial intelligence [3]. Although recent neuro-symbolic systems have achieved remarkable progress [4-7], their operation is ultimately constrained by classical computational architectures. Quantum computing [8], by contrast, enables information encoding and coherent parallelism beyond classical limits [9-14], raising the possibility of accelerating structured symbolic deduction [15]. Here we report the experimental realization of automated geometry theorem proving on a fully programmable superconducting quantum processor. We develop two complementary quantum proving frameworks. The first implements Wu's algebraic elimination method using quantum pseudo-division, with multivariate polynomials represented in superposition states, enabling quantum algebraic theorem proving. The second implements the full-angle method as backward symbolic reasoning through a hybrid quantum strategy-guided architecture, demonstrating a general route toward quantum symbolic proof search. As illustrative examples, we prove two theorems on a superconducting quantum processor: the perpendicularity of the diagonals of a square and a 1978 International Mathematical Olympiad geometry problem. Our results establish, at the experimental level, automated logical reasoning as a viable task for near-term quantum processors and provide a concrete pathway toward quantum-enhanced symbolic intelligence.

quant-ph↗

arXiv2026

A superconducting surface-code processor with lattice-surgery logical operations

Fault-tolerant logical operations are fundamental for scalable quantum computation. Here, we report the experimental realization of lattice-surgery operations between a pair of distance-three surface-code logical qubits on a planar superconducting processor. During repeated syndrome extraction cycles, the logical qubits exhibit per-cycle error rates of $0.0365(2)$ and $0.0282(1)$, respectively, after leakage events are rejected. By leveraging joint initialization and lattice splitting, we deterministically prepare a logical Bell state, confirming genuine bipartite entanglement via the error-corrected logical state fidelity. We further execute a two-qubit Deutsch-Jozsa algorithm at the logical level to demonstrate algorithmic utility in a fault-tolerant framework. Finally, to achieve universal control, we implement magic-state injection and gate teleportation to realize continuous non-Clifford rotations about the logical $X$ axis. For the logical $R_{X}(π/4)$ gate, we achieve a logical gate fidelity of $0.943_{-9}^{+10}$ conditioned on the absence of detected errors. These results establish lattice surgery as a practical and versatile paradigm for logical computation in near-term surface-code architectures, representing a critical milestone toward scalable fault-tolerant quantum advantage in superconducting circuits.

quant-ph↗

arXiv2026

Fock space prethermalization and time-crystalline order on a quantum processor

Periodically driven quantum many-body systems exhibit a wide variety of exotic nonequilibrium phenomena and provide a promising pathway for quantum applications. A fundamental challenge for stabilizing and harnessing these highly entangled states of matter is system heating by energy absorption from the drive. Here, we propose and demonstrate a disorder-free mechanism, dubbed Fock space prethermalization (FSP), to suppress heating. This mechanism divides the Fock-space network into linearly many sparse sub-networks, thereby prolonging the thermalization timescale even for initial states at high energy densities. Using 72 superconducting qubits, we observe an FSP-based time-crystalline order that persists over 120 cycles for generic initial Fock states. The underlying kinetic constraint of approximately conserved domain wall (DW) numbers is identified by measuring site-resolved correlators. Further, we perform finite-size scaling analysis for DW and Fock-space dynamics by varying system sizes, which reveals size-independent regimes for FSP-thermalization crossover and links the dynamical behaviors to the eigenstructure of the Floquet unitary. Our work establishes FSP as a robust mechanism for breaking ergodicity, and paves the way for exploring novel nonequilibrium quantum matter and its applications.

quant-ph↗

arXiv2026

Teleportation transition of surface codes on a superconducting quantum processor

The topological surface code is a leading candidate for harnessing long-range entanglement to protect logical quantum information against errors, and teleportation of logical states is desirable for robust quantum information processing. Nevertheless, scaling up the surface code in quantum teleportation poses a formidable challenge to experiment. Here on a superconducting quantum processor with 125 qubits, we demonstrate the robust teleportation of topological rotated surface code prepared by a linear-depth unitary circuit, with code distances up to 7. We obtain the teleportation phase diagram by tuning the local entangling gates uniformly across a finite threshold. Furthermore, we show that the entangling threshold can be boosted by coherent qubit rotations that inject magic resources beyond the Clifford regime, restoring the duality symmetry of the topological phase, which serves as a guiding principle to minimize the entanglement resource. Our results shed light on simulating and leveraging topological quantum matter on quantum devices, and pave the way to the ultimate goal of distributed fault tolerant quantum computation.

quant-ph↗

arXiv2025

Combinatorial optimization enhanced by shallow quantum circuits with 104 superconducting qubits

A pivotal task for quantum computing is to speed up solving problems that are both classically intractable and practically valuable. Among these, combinatorial optimization problems have attracted tremendous attention due to their broad applicability and natural fitness to Ising Hamiltonians. Here we propose a quantum sampling strategy, based on which we design an algorithm for accelerating solving the ground states of Ising model, a class of NP-hard problems in combinatorial optimization. The algorithm employs a hybrid quantum-classical workflow, with a shallow-circuit quantum sampling subroutine dedicated to navigating the energy landscape. Using up to 104 superconducting qubits, we demonstrate that this algorithm outputs favorable solutions against even a highly-optimized classical simulated annealing (SA) algorithm. Furthermore, we illustrate the path toward quantum speedup based on the time-to-solution metric against SA running on a single-core CPU with just 100 qubits. Our results indicate a promising alternative to classical heuristics for combinatorial optimization, a paradigm where quantum advantage might become possible on near-term superconducting quantum processors with thousands of qubits and without the assistance of error correction.

quant-ph↗

arXiv2025

Demonstration of low-overhead quantum error correction codes

Quantum computers hold the potential to surpass classical computers in solving complex computational problems. However, the fragility of quantum information and the error-prone nature of quantum operations make building large-scale, fault-tolerant quantum computers a prominent challenge. To combat errors, pioneering experiments have demonstrated a variety of quantum error correction codes. Yet, most of these codes suffer from low encoding efficiency, and their scalability is hindered by prohibitively high resource overheads. Here, we report the demonstration of two low-overhead quantum low-density parity-check (qLDPC) codes, a distance-4 bivariate bicycle code and a distance-3 qLDPC code, on our latest superconducting processor, Kunlun, featuring 32 long-range-coupled transmon qubits. Utilizing a two-dimensional architecture with overlapping long-range couplers, we demonstrate simultaneous measurements of all nonlocal weight-6 stabilizers via the periodic execution of an efficient syndrome extraction circuit. We achieve a logical error rate per logical qubit per cycle of $(8.91 \pm 0.17)\%$ for the distance-4 bivariate bicycle code with four logical qubits and $(7.77 \pm 0.12)\%$ for the distance-3 qLDPC code with six logical qubits. Our results establish the feasibility of implementing various qLDPC codes with long-range coupled superconducting processors, marking a crucial step towards large-scale low-overhead quantum error correction.

quant-ph↗

arXiv2025

Demonstrating quantum error mitigation on logical qubits

A long-standing challenge in quantum computing is developing technologies to overcome the inevitable noise in qubits. To enable meaningful applications in the early stages of fault-tolerant quantum computing, devising methods to suppress post-correction logical failures is becoming increasingly crucial. In this work, we propose and experimentally demonstrate the application of zero-noise extrapolation, a practical quantum error mitigation technique, to error correction circuits on state-of-the-art superconducting processors. By amplifying the noise on physical qubits, the circuits yield outcomes that exhibit a predictable dependence on noise strength, following a polynomial function determined by the code distance. This property enables the effective application of polynomial extrapolation to mitigate logical errors. Our experiments demonstrate a universal reduction in logical errors across various quantum circuits, including fault-tolerant circuits of repetition and surface codes. We observe a favorable performance in multi-round error correction circuits, indicating that this method remains effective when the circuit depth increases. These results advance the frontier of quantum error suppression technologies, opening a practical way to achieve reliable quantum computing in the early fault-tolerant era.

quant-ph↗

arXiv2025

Observation of topological prethermal strong zero modes

Symmetry-protected topological phases cannot be described by any local order parameter and are beyond the conventional symmetry-breaking paradigm for understanding quantum matter. They are characterized by topological boundary states robust against perturbations that respect the protecting symmetry. In a clean system without disorder, these edge modes typically only occur for the ground states of systems with a bulk energy gap and would not survive at finite temperatures due to mobile thermal excitations. Here, we report the observation of a distinct type of topological edge modes, which are protected by emergent symmetries and persist even up to infinite temperature, with an array of 100 programmable superconducting qubits. In particular, through digital quantum simulation of the dynamics of a one-dimensional disorder-free "cluster" Hamiltonian, we observe robust long-lived topological edge modes over up to 30 cycles at a wide range of temperatures. By monitoring the propagation of thermal excitations, we show that despite the free mobility of these excitations, their interactions with the edge modes are substantially suppressed in the dimerized regime due to an emergent U(1)$\times$U(1) symmetry, resulting in an unusually prolonged lifetime of the topological edge modes even at infinite temperature. In addition, we exploit these topological edge modes as logical qubits and prepare a logical Bell state, which exhibits persistent coherence in the dimerized and off-resonant regime, despite the system being disorder-free and far from its ground state. Our results establish a viable digital simulation approach to experimentally exploring a variety of finite-temperature topological phases and demonstrate a potential route to construct long-lived robust boundary qubits that survive to infinite temperature in disorder-free systems.

quant-ph↗

arXiv2025

Exploring nontrivial topology at quantum criticality in a superconducting processor

The discovery of nontrivial topology in quantum critical states has introduced a new paradigm for classifying quantum phase transitions and challenges the conventional belief that topological phases are typically associated with a bulk energy gap. However, realizing and characterizing such topologically nontrivial quantum critical states with large particle numbers remains an outstanding experimental challenge in statistical and condensed matter physics. Programmable quantum processors can directly prepare and manipulate exotic quantum many-body states, offering a powerful path for exploring the physics behind these states. Here, we present an experimental exploration of the critical cluster Ising model by preparing its low-lying critical states on a superconducting processor with up to $100$ qubits. We develop an efficient method to probe the boundary $g$-function based on prepared low-energy states, which allows us to uniquely identify the nontrivial topology of the critical systems under study. Furthermore, by adapting the entanglement Hamiltonian tomography technique, we recognize two-fold topological degeneracy in the entanglement spectrum under periodic boundary condition, experimentally verifying the universal bulk-boundary correspondence in topological critical systems. Our results demonstrate the low-lying critical states as useful quantum resources for investigating the interplay between topology and quantum criticality.

quant-ph↗

arXiv2024

Precision-Aware Iterative Algorithms Based on Group-Shared Exponents of Floating-Point Numbers

Iterative solvers are frequently used in scientific applications and engineering computations. However, the memory-bound Sparse Matrix-Vector (SpMV) kernel computation hinders the efficiency of iterative algorithms. As modern hardware increasingly supports low-precision computation, the mixed-precision optimization of iterative algorithms has garnered widespread attention. Nevertheless, existing mixed-precision methods pose challenges, including format conversion overhead, tight coupling between storage and computation representation, and the need to store multiple precision copies of data. This paper proposes a floating-point representation based on the group-shared exponent and segmented storage of the mantissa, enabling higher bit utilization of the representation vector and fast switches between different precisions without needing multiple data copies. Furthermore, a stepped mixed-precision iterative algorithm is proposed. Our experimental results demonstrate that, compared with existing floating-point formats, our approach significantly improves iterative algorithms' performance and convergence residuals.

cs.DC↗