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Jiezhi Chen

Publications and source records attributed to Jiezhi Chen.

4 recordsLinked to original sources

A substrate booster for P-type 2D ferromagnetic semiconductor

Spin transistors with its both charge and spin properties tuned via electrostatic gating are believed capable for widespread use, which however have proven challenging due to the extreme rareness of their physical base -- magnetic semiconductors. The latter are limited within very few systems including diluted magnetic semiconductors (DMS) and two-dimensional ferromagnetic semiconductors (2D-FMS), and known to suffer from inadequate gate-tunability of their electric and/or magnetic properties. Here, we show a substrate engineering paradigm by interfacing few-layered Cr$_{2}$Ge$_{2}$Te$_{6}$ (FL-CGT) with an antiferromagnetic insulator CrOCl. Owing to the subtle interfacial charge transfer couplings, CGT can be drastically turned from an ambipolar semiconductor into a high performance P-type semiconductor. When cooled below the Curie temperature, the ON-OFF ratio in such substrate-boosted FMS field-effect transistor (FET) reaches 10$^{5}$ with its coercive field $H_{c}$ of magnetic hysteresis loop tunable by a factor of more than 200$\%$, enabling {gate-assisted magnetic switching in the prototype semiconducting spin transistor architecture}. A crossover from critical power-law scaling to a dual power-law behaviour under heavy hole doping was further observed. Our findings {signify} an efficient interfacial charge transfer and electrically modulated magnetic anisotropy energy supported by calculations. This high performance P-type FMS-FET system suggests that active substrate-boosting paradigm might be a powerful path for the investigation of future gate-tunable spintronic devices.

cond-mat.mes-hall↗

A Measurement Study of Model Context Protocol Ecosystem

The Model Context Protocol (MCP) has been proposed as a unifying standard for connecting large language models (LLMs) with external tools and resources, promising the same role for AI integration that HTTP and USB played for the Web and peripherals. Yet, despite rapid adoption and hype, its trajectory remains uncertain. Are MCP marketplaces truly growing, or merely inflated by placeholders and abandoned prototypes? Are servers secure and privacy-preserving, or do they expose users to systemic risks? And do clients converge on standardized protocols, or remain fragmented across competing designs? In this paper, we present the first large-scale empirical study of the MCP ecosystem. We design and implement MCPCrawler, a systematic measurement framework that collects and normalizes data from six major markets. Over a 14-day campaign, MCPCrawler aggregated 17,630 raw entries, of which 8,401 valid projects (8,060 servers and 341 clients) were analyzed. Our results reveal that more than half of listed projects are invalid or low-value, that servers face structural risks including dependency monocultures and uneven maintenance, and that clients exhibit a transitional phase in protocol and connection patterns. Together, these findings provide the first evidence-based view of the MCP ecosystem, its risks, and its future trajectory.

cs.CY↗

Operation Scheme Optimizations to Achieve Ultra-high Endurance (1010) in Flash Memory with Robust Reliabilities

Flash memory has been widely adopted as stand-alone memory and embedded memory due to its robust reliability. However, the limited endurance obstacles its further applications in storage class memory (SCM) and to proceed endurance-required computing-in-memory (CIM) tasks. In this work, the optimization strategies have been studied to tackle this concern. It is shown that by adopting the channel hot electrons injection (CHEI) and hot hole injection (HHI) to implement program/erase (PE) cycling together with a balanced memory window (MW) at the high-Vth (HV) mode, impressively, the endurance can be greatly extended to 1010 PE cycles, which is a record-high value in flash memory. Moreover, by using the proposed electric-field-assisted relaxation (EAR) scheme, the degradation of flash cells can be well suppressed with better subthreshold swings (SS) and lower leakage currents (sub-10pA after 1010 PE cycles). Our results shed light on the optimization strategy of flash memory to serve as SCM and implementendurance-required CIM tasks.

eess.SY↗

A gate-programmable van der Waals metal-ferroelectric-semiconductor memory

Ferroelecticity, one of the keys to realize nonvolatile memories owing to the remanent electric polarization, has been an emerging phenomenon in the two-dimensional (2D) limit. Yet the demonstrations of van der Waals (vdW) memories using 2D ferroelectric materials as an ingredient are very limited. Especially, gate-tunable ferroelectric vdW memristive device, which holds promises in future neuromorphic applications, remains challenging. Here, we show a prototype gate-programmable memory by vertically assembling graphite, CuInP2S6, and MoS2 layers into a metal-ferroelectric-semiconductor architecture. The resulted devices exhibit two-terminal switchable electro-resistance with on-off ratios exceeding 105 and long-term retention, akin to a conventional memristor but strongly coupled to the ferroelectric characteristics of the CuInP2S6 layer. By controlling the top gate, Fermi level of MoS2 can be set inside (outside) of its band gap to quench (enable) the memristive behaviour, yielding a three-terminal gate programmable nonvolatile vdW memory. Our findings pave the way for the engineering of ferroelectric-mediated memories in future implementations of nanoelectronics.

cond-mat.mtrl-sci↗