Jin-yuan Wu | Searcharxiv

arXiv2026

A Full Rank Pileup Deconvolution Scheme Suitable for Calorimeter Online Trigger Primitive Generation

In this document, a pileup deconvolution scheme not relying on any mathematics guessing is presented. In high energy physics experiment, as the luminosity increases, pile-up issues on detectors such as calorimeters become non-negligible. Deconvolution approaches developed for data taken from DAQ systems are usually rank-deficient or underdetermined, having less equations than unknowns, even with the ADC values from multiple beam crossings are collected. These deconvolution approaches need mathematic pre-assumptions such as Sparse Representation. For online computation tasks such as for trigger primitive creation, signal availability is significantly different as in offline data analysis stage, and therefore, it is possible to use different (yet simpler) algorithms. In this situation, number of ADC values of the calorimeter outputs is the same as the number of beam crossings (or 4 times number of beam crossings, depending on the ADC sampling rate), and therefore, the number of equations can be arranged to be the same as number of unknowns. This way, a determined deconvolution scheme with a full-rank squared convolution (and deconvolution) matrix becomes possible. The robustness of deconvolution over long time windows is also studied in this paper.

physics.ins-det↗

arXiv2025

An Arbitrary Time Interval Generator Base on Vernier Clocks with 0.67 ps Adjustable Steps Implemented in FPGA

In TDC testing or timing system implementation tasks, it is often desirable to generate signal pulses with fine adjustable time intervals. In delay cell-based schemes, the time adjustment steps are limited by the propagation delays of the cells, which are typically 15 to 20 picoseconds per step and are sensitive to temperature and operating voltage. In this document, a purely digital scheme based on two vernier clocks with small frequency difference generated using cascaded PLL is reported. The scheme is tested in two families of low-cost FPGA and 0.67 and 0.97 picoseconds adjustable steps of the time intervals are achieved.

physics.ins-det↗