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Jincong Lu

Publications and source records attributed to Jincong Lu.

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WarPGNN: A Parametric Thermal Warpage Analysis Framework with Physics-aware Graph Neural Network

With the advent of system-in-package (SiP) chiplet-based design and heterogeneous 2.5D/3D integration, thermal-induced warpage has become a critical reliability concern. While conventional numerical approaches can deliver highly accurate results, they often incur prohibitively high computational costs, limiting their scalability for complex chiplet-package systems. In this paper, we present WarPGNN, an efficient and accurate parametric thermal warpage analysis framework powered by Graph Neural Networks (GNNs). By operating directly on graphs constructed from the floorplans, WarPGNN enables fast warpage-aware floorplan exploration and exhibits strong transferability across diverse package configurations. Our method first encodes multi-die floorplans into reduced Transitive Closure Graphs (rTCGs), then a Graph Convolution Network (GCN)-based encoder extracts hierarchical structural features, followed by a U-Net inspired decoder that reconstructs warpage maps from graph feature embeddings. Furthermore, to address the long-tailed pattern of warpage data distribution, we developed a physics-informed loss and revised a message-passing encoder based on Graph Isomorphic Network (GIN) that further enhance learning performance for extreme cases and expressiveness of graph embeddings. Numerical results show that WarPGNN achieves more than 205.91x speedup compared with the 2-D efficient FEM-based method and over 119766.64x acceleration with 3-D FEM method COMSOL, respectively, while maintaining comparable accuracy at only 1.26% full-scale normalized RMSE and 2.21% warpage value error. Compared with recent DeepONet-based model, our method achieved comparable prediction accuracy and inference speedup with 3.4x lower training time. In addition, WarPGNN demonstrates remarkable transferability on unseen datasets with up to 3.69% normalized RMSE and similar runtime.

cs.AR

Enhanced Hybrid Temporal Computing Using Deterministic Summations for Ultra-Low-Power Accelerators

This paper presents an accuracy-enhanced Hybrid Temporal Computing (E-HTC) framework for ultra-low-power hardware accelerators with deterministic additions. Inspired by the recently proposed HTC architecture, which leverages pulse-rate and temporal data encoding to reduce switching activity and energy consumption but loses accuracy due to its multiplexer (MUX)-based scaled addition, we propose two bitstream addition schemes: (1) an Exact Multiple-input Binary Accumulator (EMBA), which performs precise binary accumulation, and (2) a Deterministic Threshold-based Scaled Adder (DTSA), which employs threshold logic for scaled addition. These adders are integrated into a multiplier accumulator (MAC) unit supporting both unipolar and bipolar encodings. To validate the framework, we implement two accelerators: a Finite Impulse Response (FIR) filter and an 8-point Discrete Cosine Transform (DCT)/iDCT engine. Results on a 4x4 MAC show that, in unipolar mode, E-HTC matches the RMSE of state-of-the-art Counter-Based Stochastic Computing (CBSC) MAC, improves accuracy by 94% over MUX-based HTC, and reduces power and area by 23% and 7% compared to MUX-based HTC and 64% and 74% compared to CBSC. In bipolar mode, E-HTC MAC achieves 2.09% RMSE -- an 83% improvement over MUX-based HTC -- and approaches CBSC's 1.40% RMSE with area and power savings of 28% and 43% vs. MUX-based HTC and about 76% vs. CBSC. In FIR experiments, both E-HTC variants yield PSNR gains of 3--5 dB (30--45% RMSE reduction) while saving 13% power and 3% area. For DCT/iDCT, E-HTC boosts PSNR by 10--13 dB (70--75% RMSE reduction) while saving area and power over both MUX- and CBSC-based designs.

cs.AR