arXiv subjects

Jinhyun Noh

Publications and source records attributed to Jinhyun Noh.

3 recordsLinked to original sources

arXiv2022

A Gate-All-Around Single-Channel In2O3 Nanoribbon FET with Near 20 mA/μm Drain Current

In this work, we demonstrate atomic-layer-deposited (ALD) single-channel indium oxide (In2O3) gate-all-around (GAA) nanoribbon FETs in a back-end-of-line (BEOL) compatible process. A maximum on-state current (ION) of 19.3 mA/μm (near 20 mA/μm) is achieved in an In2O3 GAA nanoribbon FET with a channel thickness (TIO) of 3.1 nm, channel length (Lch) of 40 nm, channel width (Wch) of 30 nm and dielectric HfO2 of 5 nm. The record high drain current obtained from an In2O3 FET is about one order of magnitude higher than any conventional single-channel semiconductor FETs. This extraordinary drain current and its related on-state performance demonstrate ALD In2O3 is a promising oxide semiconductor channel with great opportunities in BEOL compatible monolithic 3D integration.

physics.app-ph↗

arXiv2021

First Demonstration of Robust Tri-Gate \b{eta}-Ga2O3 Nano-membrane Field-Effect Transistors Operated Up to 400 °C

Nano-membrane tri-gate beta-gallium oxide (\b{eta}-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with a 50 nm fin structure. For high-quality interface between \b{eta}-Ga2O3 and gate dielectric, atomic layer-deposited 15-nm-thick aluminum oxide (Al2O3) was utilized with Tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV/dec, high drain current (IDS) ON/OFF ratio of 1.5 X 109, and negligible transfer characteristic hysteresis. We also experimentally demonstrated robustness of these devices with current-voltage (I-V) characteristics measured at temperatures up to 400 °C.

physics.app-ph↗

arXiv2017

Thermodynamic Studies of \b{eta}-Ga2O3 Nanomembrane Field-Effect Transistors on a Sapphire Substrate

The self-heating effect is a severe issue for high-power semiconductor devices, which degrades the electron mobility and saturation velocity, and also affects the device reliability. On applying an ultrafast and high-resolution thermoreflectance imaging technique, the direct self-heating effect and surface temperature increase phenomenon are observed on novel top-gate \b{eta}-Ga2O3 on insulator field-effect transistors. Here, we demonstrate that by utilizing a higher thermal conductivity sapphire substrate rather than a SiO2/Si substrate, the temperature rise above room temperature of \b{eta}-Ga2O3 on the insulator field-effect transistor can be reduced by a factor of 3 and thereby the self-heating effect is significantly reduced. Both thermoreflectance characterization and simulation verify that the thermal resistance on the sapphire substrate is less than 1/3 of that on the SiO2/Si substrate. Therefore, maximum drain current density of 535 mA/mm is achieved on the sapphire substrate, which is 70% higher than that on the SiO2/Si substrate due to reduced self-heating. Integration of \b{eta}-Ga2O3 channel on a higher thermal conductivity substrate opens a new route to address the low thermal conductivity issue of \b{eta}-Ga2O3 for power electronics applications.

physics.app-ph↗