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Joe Driscoll

Publications and source records attributed to Joe Driscoll.

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Real-time Digital RF Emulation -- I: The Direct Path Computational Model

In this paper we consider the problem of developing a computational model for emulating an RF channel. The motivation for this is that an accurate and scalable emulator has the potential to minimize the need for field testing, which is expensive, slow, and difficult to replicate. Traditionally, emulators are built using a tapped delay line model where long filters modeling the physical interactions of objects are implemented directly. For an emulation scenario consisting of $M$ objects all interacting with one another, the tapped delay line model's computational requirements scale as $O(M^3)$ per sample: there are $O(M^2)$ channels, each with $O(M)$ complexity. In this paper, we develop a new ``direct path" model that, while remaining physically faithful, allows us to carefully factor the emulator operations, resulting in an $O(M^2)$ per sample scaling of the computational requirements. The impact of this is drastic, a $200$ object scenario sees about a $100\times$ reduction in the number of per sample computations. Furthermore, the direct path model gives us a natural way to distribute the computations for an emulation: each object is mapped to a computational node, and these nodes are networked in a fully connected communication graph. Alongside a discussion of the model and the physical phenomena it emulates, we show how to efficiently parameterize antenna responses and scattering profiles within this direct path framework. To verify the model and demonstrate its viability in hardware, we provide several numerical experiments produced using a cycle level C++ simulator of a hardware implementation of the model.

eess.SP

Real-time Digital RF Emulation -- II: A Near Memory Custom Accelerator

A near memory hardware accelerator, based on a novel direct path computational model, for real-time emulation of radio frequency systems is demonstrated. Our evaluation of hardware performance uses both application-specific integrated circuits (ASIC) and field programmable gate arrays (FPGA) methodologies: 1). The ASIC testchip implementation, using TSMC 28nm CMOS, leverages distributed autonomous control to extract concurrency in compute as well as low latency. It achieves a $518$ MHz per channel bandwidth in a prototype $4$-node system. The maximum emulation range supported in this paradigm is $9.5$ km with $0.24$ $μ$s of per-sample emulation latency. 2). The FPGA-based implementation, evaluated on a Xilinx ZCU104 board, demonstrates a $9$-node test case (two Transmitters, one Receiver, and $6$ passive reflectors) with an emulation range of $1.13$ km to $27.3$ km at $215$ MHz bandwidth.

eess.SP

Deformations of Asymptotically Conical $G_2$-Instantons

We develop the deformation theory of instantons on asymptotically conical $G_2$-manifolds, where an asymptotic connection at infinity is fixed. A spinorial approach is adopted to relate the space of deformations to the kernel of a twisted Dirac operator on the $G_2$-manifold and to the eigenvalues of a twisted Dirac operator on the nearly Kähler link. This framework is then used to calculate the virtual dimension of the moduli spaces of $G_2$-instantons on which several known examples live. One such example considered is the $G_2$-instanton of Günaydin-Nicolai, which lives on $R^7$. As an application of the deformation theory, we show how knowledge of the virtual dimension of the moduli space allows us to prove that unobstructed connections in the moduli space are $G_2$-invariant. By classifying such connections we prove a uniqueness result for unobstructed $G_2$-instantons on the principal $G_2$-bundle over $R^7$.

math.DG