arXiv subjects

Joel Hätinen

Publications and source records attributed to Joel Hätinen.

5 recordsLinked to original sources

arXiv2026

Electronic cooling of a TiW alloy normal-metal island using Nb-based superconducting tunnel junctions

TiW thin films remain non-superconducting down to millikelvin temperatures and are compatible with large-scale CMOS manufacturing, making them attractive for cryogenic and quantum tunnel-junction devices, such as normal-metal-insulator-superconductor (NIS) thermal sensors and electron refrigerators. We demonstrate significant electronic cooling of a TiW-based normal-metal island and electron thermometry by using TiW-Al-AlOx-Nb NIS tunnel-junction stacks. The NIS thermometer enables local electron temperature measurements from 0.5 to 8.32 K. NIS cooling is observed between 0.6 and 3.5 K, with maximum absolute and relative temperature reductions of 217 mK and 27%, respectively. Calculations using tunnel-junction parameters obtained independently from current-voltage fits reproduce the measured optimum-voltage scale, which lies substantially below the ideal low-temperature prediction.

cond-mat.mes-hall↗

arXiv2026

Phonon-blocked junction calorimeter

This study introduces the theory of a microcalorimeter based on phonon-blocked superconducting tunnel junctions, integrating on-chip electron cooling and boundary resistance phonon isolation to achieve exceptional energy resolution and rapid thermal response. A general theoretical framework is presented, along with derived approximate analytical expressions for key performance metrics, including cooling factor, thermal time constant, noise equivalent power and energy resolution. The work examines the influence of device parameters, including non-ideal effects such as subgap tunneling and heat backflow, and offers insights into optimizing the detector performance. The findings highlight the potential of the phonon-blocked junction microcalorimeters to rival or even outperform state-of-the-art technologies such as transition-edge sensors, paving the way for applications requiring precise and fast energy spectroscopy.

physics.ins-det↗

arXiv2025

Native-oxide-passivated trilayer junctions for superconducting qubits

Superconducting qubits in today's quantum processing units are typically fabricated with angle-evaporated aluminum--aluminum-oxide--aluminum Josephson junctions. However, there is an urgent need to overcome the limited reproducibility of this approach when scaling up the number of qubits and junctions. Fabrication methods based on subtractive patterning of superconductor--insulator--superconductor trilayers, used for more classical large-scale Josephson junction circuits, could provide the solution but they in turn often suffer from lossy dielectrics incompatible with high qubit coherence. In this work, we utilize native aluminum oxide as a sidewall passivation layer for junctions based on aluminum--aluminum-oxide--niobium trilayers, and use such junctions in qubits. We design the fabrication process such that the few-nanometer-thin native oxide is not exposed to oxide removal steps that could increase its defect density or hinder its ability to prevent shorting between the leads of the junction. With these junctions, we design and fabricate transmon-like qubits and measure time-averaged coherence times up to 30 $μ$s at a qubit frequency of 5 GHz, corresponding to a qubit quality factor of one million. Our process uses subtractive patterning and optical lithography on wafer scale, enabling high throughput in patterning. This approach provides a scalable path toward fabrication of superconducting qubits on industry-standard platforms.

quant-ph↗

arXiv2024

Scalable on-chip multiplexing of silicon single and double quantum dots

Owing to the maturity of complementary metal oxide semiconductor (CMOS) microelectronics, qubits realized with spins in silicon quantum dots (QDs) are considered among the most promising technologies for building scalable quantum computers. For this goal, ultra-low-power on-chip cryogenic CMOS (cryo-CMOS) electronics for control, read-out, and interfacing of the qubits is an important milestone. We report on-chip interfacing of tunable electron and hole QDs by a 64-channel cryo-CMOS multiplexer with less-than-detectable static power dissipation. We analyze charge noise and measure state-of-the-art addition energies and gate lever arm parameters in the QDs. We correlate low noise in QDs and sharp turn-on characteristics in cryogenic transistors, both fabricated with the same gate stack. Finally, we demonstrate that our hybrid quantum-CMOS technology provides a route to scalable interfacing of a large number of QD devices, enabling, for example, variability analysis and QD qubit geometry optimization, which are prerequisites for building large-scale silicon-based quantum computers.

cond-mat.mes-hall↗

arXiv2023

Thermal resistance in superconducting flip-chip assemblies

Cryogenic microsystems that utilize different 3D integration techniques are being actively developed, e.g., for the needs of quantum technologies. 3D integration can introduce opportunities and challenges to the thermal management of low temperature devices. In this work, we investigate sub-1 K inter-chip thermal resistance of a flip-chip bonded assembly, where two silicon chips are interconnected by compression bonding via indium bumps. The total thermal contact area between the chips is 0.306 mm$^2$ and we find that the temperature dependence of the inter-chip thermal resistance follows the power law of $αT^{-3}$, with $α= 7.7-15.4$ K$^4$$μ$m$^2$/nW. The $T^{-3}$ relation indicates phononic interfacial thermal resistance, which is supported by the vanishing contribution of the electrons to the thermal conduction, due to the superconducting interconnections. Such a thermal resistance value can introduce a thermalization bottleneck in particular at cryogenic temperatures. This can be detrimental for some applications, yet it can also be harnessed. We provide an example of both cases by estimating the parasitic overheating of a cryogenic flip-chip assembly operated under various heat loads as well as simulate the performance of solid-state junction microrefrigerators utilizing the observed thermal isolation.

physics.app-ph↗