arXiv subjects

Johan Swerts

Publications and source records attributed to Johan Swerts.

6 recordsLinked to original sources

arXiv2025

NiSi$_2$ as seed layer for epitaxial growth of NiAl and Cr on Si(001)

In general, metal layers cannot be grown epitaxially on Si due to the tendency of metals to react and form a silicide. Even in case the metal layer has a matching lattice symmetry and atomic distance, the Si/metal interface is disturbed by the silicide thus preventing epitaxial growth. One exception is NiAl which is known to grow epitaxially when deposited on Si(001). During the growth, NiAl reacts with Si to form NiSi$_2$. In this work, epitaxial NiAl is grown and significant silicidation is observed in accordance with previous reports. However, the role that this silicide plays as a template for the epitaxial growth of NiAl has not been clear to this date. We hypothesize that NiSi$_2$ acts as a necessary seed layer between the Si substrate and the NiAl layer. Additionally, NiSi$_2$ can be used as a seed layer for the epitaxial growth of other metals besides NiAl. This was tested by growing NiSi$_2$ seperately and replacing the NiAl layer with Cr. Growing Cr directly on Si(001) produced a polycrystalline layer. When NiSi$_2$ was used as a seed layer, the Cr layer was found to be a single crystal with Si(001)//Cr(001) and Si(100)//Cr(100). NiSi was also tried as seed layer for Cr and was found to produce a polycrystalline Cr layer. Using NiSi$_2$ as a seed layer could enable the growth of various epitaxial materials for industrial semiconductor applications.

cond-mat.mtrl-sci↗

arXiv2024

Selecting Alternative Metals for Advanced Interconnects

Interconnect resistance and reliability have emerged as critical factors limiting the performance of advanced CMOS circuits. With the slowdown of transistor scaling, interconnect scaling has become the primary driver of continued circuit miniaturization. The associated scaling challenges for interconnects are expected to further intensify in future CMOS technology nodes. As interconnect dimensions approach the 10 nm scale, the limitations of conventional Cu dual-damascene metallization are becoming increasingly difficult to overcome, spurring over a decade of focused research into alternative metallization schemes. The selection of alternative metals is a highly complex process, requiring consideration of multiple criteria, including resistivity at reduced dimensions, reliability, thermal performance, process technology readiness, and sustainability. This tutorial introduces the fundamental criteria for benchmarking and selecting alternative metals and reviews the current state of the art in this field. It covers materials nearing adoption in high-volume manufacturing, materials currently under active research, and potential future directions for fundamental study. While early alternatives to Cu metallization have recently been introduced in commercial CMOS devices, the search for the optimal interconnect metal remains ongoing.

physics.app-ph↗

arXiv2024

Cu$_x$Al$_{1-x}$ films as Alternatives to Copper for Advanced Interconnect Metallization

Cu$_x$Al$_{1-x}$ thin films with $0.2 \le x \le 0.7$ have been studied as potential alternatives for the metallization of advanced interconnects. First-principles simulations were used to obtain the Cu$_x$Al$_{1-x}$ electronic structure and cohesive energy to benchmark different intermetallics and their prospects for interconnect metallization. Next, thin Cu$_x$Al$_{1-x}$ films were deposited by PVD with thicknesses in the range between 3 and 28 nm. The lowest resistivities of 9.5 $μΩ$cm were obtained for 28 nm thick stochiometric CuAl and CuAl$_2$ after 400$^\circ$C post-deposition annealing. Based on the experimental results, we discuss the main challenges for the studied aluminides from an interconnect point of view, namely the control of the film stoichiometry, the phase separation observed for off-stoichiometric CuAl and CuAl$_2$, as well as the presence of a nonstoichiometric surface oxide.

cond-mat.mtrl-sci↗

arXiv2024

Al$_3$Sc thin films for advanced interconnect applications

Al$_x$Sc$_{1-x}$ thin films have been studied with compositions around Al$_3$Sc ($x$ = 0.75) for potential interconnect metallization applications. As-deposited 25 nm thick films were x-ray amorphous but crystallized at 190°C, followed by recrystallization at 440°C. After annealing at 500°C, 24 nm thick stoichiometric Al$_3$Sc showed a resistivity of 12.6 $μΩ$cm, limited by a combination of grain boundary and point defect (disorder) scattering. Together with ab initio calculations that found a mean free path of the charge carriers of 7 nm for stoichiometric Al$_3$Sc, these results indicate that Al$_3$Sc bears promise for future interconnect metallization schemes. Challenges remain in minimizing the formation of secondary phases as well as in the control of the non-stoichiometric surface oxidation and interfacial reactions with underlying dielectrics.

cond-mat.mtrl-sci↗

arXiv2023

Microwave Properties of Ba-Substituted Pb(Zr$_{0.52}$Ti$_{0.48}$)O$_3$ after Chemical-Mechanical Polishing

We have studied the effect of chemical-mechanical polishing (CMP) on the ferroelectric, piezoelectric, and microwave dielectric properties of Ba-substituted PZT (BPZT), deposited by pulsed laser deposition. CMP allowed for the reduction of the root mean square surface roughness of 600 nm thick BPZT films from 12.1nm to 0.79 nm. Ammonium peroxide (SC-1) cleaning was effective to remove Si CMP residuals. Measurements of the ferroelectric hysteresis after CMP indicated that the ferroelectric properties of BPZT were only weakly affected by CMP, while the piezoelectric d33 coefficient and the microwave permittivity were reduced slightly by 10%. This can be attributed to the formation of a thin dead layer at the BPZT surface. Moreover, the intrinsic dielectric permittivity at microwave frequencies between 1 and 25 GHz was not influenced by CMP, whereas the dead layer series capacitance decreased by 10%. The results indicate that the CMP process can be used to smoothen the BPZT surface without affecting the film properties strongly.

physics.app-ph↗

arXiv2017

Fabrication of magnetic tunnel junctions connected through a continuous free layer to enable spin logic devices

Magnetic tunnel junctions (MTJs) interconnected via a continuous ferromagnetic free layer were fabricated for Spin Torque Majority Gate (STMG) logic. The MTJs are biased independently and show magnetoelectric response under spin transfer torque. The electrical control of these devices paves the way to future spin logic devices based on domain wall (DW) motion. In particular, it is a significant step toward the realization of a majority gate, even though further downscaling may be required. To our knowledge, this is the first fabrication of a cross-shaped free layer shared by several perpendicular MTJs. The fabrication process can be generalized to any geometry and any number of MTJs. Thus, this framework can be applied to other spin logic concepts based on magnetic interconnect. Moreover, it allows exploration of spin dynamics for logic applications

physics.app-ph↗