arXiv subjects

Josef Salzmann

Publications and source records attributed to Josef Salzmann.

4 recordsLinked to original sources

arXiv2025

Drafting and Multi-Input Switching in Digital Dynamic Timing Simulation for Multi-Input Gates

We present a prototype multi-input gate extension of the publicly available Involution Tool for accurate digital timing simulation and power analysis of integrated circuits introduced by Oehlinger et al. (Integration, 2021). Relying on discrete event simulation, the Involution Tool allows fast timing simulation of circuits made up of an arbitrary composition of supported gates, provides automatic random input stimulus generation, and supports parameter sweeping. It also enables a detailed comparison of the delay predictions obtained by different models, including pure and inertial delays as well as digitized SPICE-generated reference traces. Our extension added support for 2-input gates like NOR and NAND, by implementing novel analytic delay formulas obtained via a refined analysis of a recently proposed thresholded first-order hybrid model of such gates. The resulting formulas faithfully cover not only multi-input switching effects (also known as Charlie effects), but also the decay of short pulses (aka Drafting effects). Besides the fact that our analytic models not only allow the derivation of closed-form delay formulas for arbitrary compositions of such gates, they are also key for a strikingly simple procedure for model parametrization, i.e., for gate characterization, which only needs three characteristic delay values. Using the extended Involution Tool, we compare the delay and power predictions for some benchmarking circuits stimulated by randomly generated input traces. Overall, our results reveal considerably improved prediction accuracy compared to the original Involution Tool, without a noticeable performance penalty.

cs.OH↗

arXiv2024

Signal Prediction for Digital Circuits by Sigmoidal Approximations using Neural Networks

Investigating the temporal behavior of digital circuits is a crucial step in system design, usually done via analog or digital simulation. Analog simulators like SPICE iteratively solve the differential equations characterizing the circuits components numerically. Although unrivaled in accuracy, this is only feasible for small designs, due to the high computational effort even for short signal traces. Digital simulators use digital abstractions for predicting the timing behavior of a circuit. Besides static timing analysis, which performs corner-case analysis of critical path delays only, dynamic timing analysis provides per-transition timing information in signal traces. In this paper, we advocate a novel approach, which generalizes digital traces to traces consisting of sigmoids, each parameterized by threshold crossing time and slope. What is needed to compute the output trace of a gate is a transfer function, which determines the parameters of the output sigmoids given the parameters of the input sigmoids. Harnessing the power of artificial neural networks (ANN), we implement such transfer functions via ANNs. Using inverters and NOR as the elementary gates in a prototype implementation of a specifically tailored simulator, we demonstrate that our approach operates substantially faster than an analog simulator, while offering better accuracy than a digital simulator.

cs.AR↗

arXiv2024

A Hybrid Delay Model for Interconnected Multi-Input Gates

Dynamic digital timing analysis is a less accurate but fast alternative to highly accurate but slow analog simulations of digital circuits. It relies on gate delay models, which allow the determination of input-to-output delays of a gate on a per-transition basis. Accurate delay models not only consider the effect of preceding output transitions here but also delay variations induced by multi-input switching (MIS) effects in the case of multi-input gates. Starting out from a first-order hybrid delay model for CMOS two-input NOR gates, we develop a hybrid delay model for Muller C gates and show how to augment these models and their analytic delay formulas by a first-order interconnect. Moreover, we conduct a systematic evaluation of the resulting modeling accuracy: Using SPICE simulations, we quantify the MIS effects on the gate delays under various wire lengths, load capacitances, and input strengths for two different CMOS technologies, comparing these results to the predictions of appropriately parameterized versions of our new gate delay models. Overall, our experimental results reveal that they capture all MIS effects with a surprisingly good accuracy despite being first-order only.

cs.AR↗

arXiv2023

An Accurate Hybrid Delay Model for Multi-Input Gates

In order to facilitate the analysis of timing relations between individual transitions in a signal trace, dynamic digital timing analysis offers a less accurate but much faster alternative to analog simulations of digital circuits. This primarily requires gate delay models that also account for the fact that the input-to-output delay of a particular input transition also depends on the temporal distance to the previous output transitions. In the case of multi-input gates, the delay also experiences variations caused by multi-input switching (MIS) effects, i.e., transitions at different inputs that occur in close temporal proximity. In this paper, we advocate the development of hybrid delay models for CMOS gates obtained by replacing transistors with time-variant resistors. We exemplify our approach by applying it to a NOR gate (and, hence, to the dual NAND gate) and a Muller C gate. We analytically solve the resulting first-order differential equations with non-constant-coefficients, and derive analytic expressions for the resulting MIS gate delays. The resulting formulas not only pave the way to a sound model parametrization procedure, but are also instrumental for implementing fast and efficient digital timing simulation. By comparison with analog simulation data, we show that our models faithfully represent all relevant MIS effects. Using an implementation in the Involution Tool, we demonstrate that our model surpasses the alternative digital delay models for NOR gates known to us in terms of accuracy, with comparably short running times.

cs.OH↗