arXiv subjects

Joshua J. Wong

Publications and source records attributed to Joshua J. Wong.

3 recordsLinked to original sources

arXiv2026

Toward Topology-Optimized Foundry PDKs: A Seeded Design Framework for Multimode Interferometers

We present an end-to-end design methodology for multimode interferometer (MMI)-based photonic devices that combines parameter optimization (PO) on analytical models with seeded topology optimization (TO) to maximize performance while preserving foundry design-rule compliance. A PO seed device is further refined via seeded TO, accessing a larger design space than analytical or parameterized methods alone can reach. We validate this pipeline on a 1x2 splitter, a TE modal multiplexer, and a polarization splitter, fabricating and measuring the first two on a commercial foundry process. Seeded TO reduces the measured insertion loss of the 1x2 splitter from 0.20 to 0.14 dB and improves TE00 transmission of the modal multiplexer from -2.79 to -1.01 dB over O-band. Applying this pipeline to a commercial foundry process design kit (PDK)-provided 1x2 and 2x2 splitter improves simulated transmission and tightens the 2x2 splitting ratio from 0.524 to 0.506, along with improved fabrication robustness, offering a practical, foundry-validated route toward incorporating TO-designed components into commercial PDKs.

physics.optics↗

arXiv2026

A 0.08 pJ/bit 56 GBaud Monolithic Optical Receiver Front End for IMDD Photonic Links

We present the design, fabrication, and measurement of a monolithically integrated optical receiver analog front end, where low power operation is a primary consideration with a goal of supporting 56 Gbaud intensity modulated direct detect transceivers. The need for low-power consumption and low-noise operation motivates a monolithic, layout driven design approach which begins with circuit topology selection and analysis. Various transistor unit cell layout configurations are explored, minimizing parasitics, enabling wide analog bandwidth and reduced input referred noise. The post-layout analog front end achieves a 28.9 GHz bandwidth with a low-frequency gain of 61.7 dBΩ. This circuit was designed within the GlobalFoundries FotonixTM monolithic silicon photonics platform. The fabricated device is characterized by its DC operation, noise characteristics, and time domain behavior. The final design was validated by on-off keyed and PAM-4 electrical eye diagram measurements to 64 GBaud, consuming 9.22 mW of power from a 1.2 V supply with less than 737 nA RMS integrated input referred noise current and 0.08 pJ/bit.

physics.optics↗

arXiv2025

Seeded Topology Optimization for Commercial Foundry Integrated Photonics

We present a seeded topology optimization methodology for integrated photonic devices fabricated on foundry platforms that yields improved performance compared to traditional topology optimization. We employ blurring filters and a design rule check correction algorithm to more readily meet fabrication constraints, resulting in devices with fewer artifacts and improved correlation between simulation and measurements. A statistical study is performed on a 2D modal multiplexer, revealing that 87% of devices optimized using this strategy conform to foundry constraints, compared to 13% of devices optimized using traditional TO. We apply seeded topology optimization to an ultra-compact TE modal multiplexer, a TE mode converter, a polarization rotator, and a high-contrast grating reflector. Using this optimization strategy, the measured insertion loss of the TE mode converter was reduced from < 1.50 dB to < 0.64 dB, and the measured TE1 insertion loss of the TE modal multiplexer was reduced from < 3.95 dB to < 1.38 dB over C-band. This approach enables a two-step inverse design process, merging of physics-informed design strategies with inverse design, and ensures strict compliance with foundry constraints throughout optimization.

physics.optics↗