arXiv subjects

Joshua Viszlai

Publications and source records attributed to Joshua Viszlai.

16 recordsLinked to original sources

arXiv2026

X-Z Round Scheduling for the Surface Code with Defects under Biased Noise

Fault-tolerant Quantum Computing (FTQC) relies on Quantum Error Correction (QEC) codes that encode logical qubits across many physical qubits to detect and correct errors. The surface code is among the most widely studied codes due to its high error threshold, the existence of efficient decoders, and hardware-friendly properties: a planar, two-dimensional layout with nearest-neighbor connectivity. In practice, however, the fabrication of solid-state quantum processors introduces hardware defects, resulting in defective qubits and couplers that must be discarded. Adapting the surface code to these defects often requires measuring the $X$- and $Z$-type checks in separate rounds rather than simultaneously. In this work, we investigate the optimal $X$-to-$Z$ checks round-scheduling ratio under biased noise systems. Our results characterize how key architectural parameters, such as noise bias, code distance, and defect rate, impact the logical error rate. We provide insights into how to determine the optimal scheduling ratio directly from device calibration data, enabling manufacturers to maximize performance without extensive simulations. Our approach reduces the logical error rate by up to $4.25\times$ at a $1\%$ defect rate and up to $8.46\times$ at a $2\%$ defect rate for a distance-$13$ surface code under moderately biased noise. Furthermore, we demonstrate that the benefits of round-scheduling extend beyond the defective-hardware setting. In biased-noise architectures subject to CNOT crosstalk, separating $X$ and $Z$ measurement rounds yields up to $4.5\times$ reduction in logical error rate.

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arXiv2026

qSIEVE: Efficient qLDPC Memory via Systolic Movement in Atom Arrays

As quantum machines have scaled up in their number of qubits, significant research has turned towards increasing their fidelity with quantum error correction codes. Although promising results have been shown with the surface code, which only requires near-neighbor connections between qubits, the high qubit overhead of such local codes promises to be problematic. Consequently, recent work has explored non-local quantum LDPC (qLDPC) codes, which have good asymptotic encoding rates. Despite theoretical progress, hardware implementations of these codes has been a longstanding challenge. At the experimental level, demonstrations of movement based communication on atom arrays suggest this is a powerful new primitive to achieve non-local connectivity. Leveraging this, we present a protocol for implementing non-local qLDPC codes in hardware. Our protocol, qSIEVE, is a co-design of such codes with movement in atom arrays. qSIEVE defines a restricted family of qLDPC codes that can be implemented efficiently with systolic movement. We then quantify the utility of qSIEVE in the context of a complete fault tolerant architecture. We compare the cost of implementing benchmark programs in a standard, surface code only architecture and a mixed architecture where data is stored in qLDPC memory with qSIEVE and loaded to surface codes for computation.

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arXiv2026

ADaPT: Adaptive-window Decoding for Practical fault-Tolerance

Window decoding, first proposed to reduce decoding complexity for real-time decoding, is an essential component to realize scalable, universal-fault tolerant computation. Prior work has focused on improving throughput through parallelization and reducing reaction time via speculation on window boundaries. However, these methods use a fixed window size d, paying a fixed decoding time overhead for each window. In practice, we find this overhead of a fixed window size unnecessary in many cases due to the sparsity of average-case errors in QEC. Leveraging this insight, in this paper we propose an adaptive window decoding technique based on decoder confidence. This technique reduces the overhead in decoding time thus reducing reaction time without compromising on logical error rates. We benchmark adaptive window decoding across different codes and hardware inspired noise models. Our results show that this adaptive technique reaches the target error rate while maintaining a low decoding time overhead across different codes, and under different noise models.

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arXiv2026

Demonstration of a Logical Architecture Uniting Motion and In-Place Entanglement

We demonstrate a logical neutral atom architecture that integrates atom motion with in-place entanglement to achieve lower overheads than entangling-zone approaches. Using a 114-qubit device, we perform three proof-of-principle logical-qubit experiments. First, we implement a pre-compiled, non-scalable variant of Shor's algorithm, observing improved logical-over-physical performance, including with loss correction and leakage detection, achieving up to a 2x reduction in TVD. Second, we construct constant-depth logical CX ladders; on current hardware these execute with serial entangling operations, yet still yield 2-4x lower error for 8 and 12 logical qubits. Third, we prepare the [[16,4,4]] code and perform single-round decoding with post-processed error correction, achieving 8x improvement on logical vs physical. These results demonstrate how combining motion with in-place entanglement offers lower overhead than entangling-zone approaches.

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arXiv2026

A manufacturable surface code architecture for spin qubits with fast transversal logic

Spin qubits in silicon quantum dot arrays are a promising quantum computation platform for long-term scalability due to their small qubit footprint and compatibility with advanced semiconductor manufacturing. However, spin qubit devices face a key architectural bottleneck: the large physical footprint of readout components relative to qubits prevents a dense layout where all qubits can be measured simultaneously, complicating the implementation of quantum error correction. This challenge is offset by the platform's unique rapid shuttling capability, which can be used to transport qubits to distant readout ports. In this work, we explore the design constraints and capabilities of spin qubits in silicon and propose the SNAQ (Shuttling-capable Narrow Array of spin Qubits) surface code architecture, which relaxes the 1:1 readout-to-qubit assumption by leveraging spin shuttling to time-multiplex ancilla qubit initialization and readout. Our analysis shows that, given sufficiently high (experimentally demonstrated) qubit coherence times, SNAQ delivers an orders-of-magnitude reduction in chip area per logical qubit. Additionally, by using a denser grid of physical qubits, SNAQ enables fast transversal logic for short-distance logical operations, achieving over 10x improvement in local logical clock speed while still supporting global operations via lattice surgery. This translates to a 3.2-5.7x improvement in key Adder and Lookup fault-tolerant subroutines. Our work pinpoints critical hardware metrics and provides a compelling path toward high-performance fault-tolerant computation on near-term-manufacturable spin qubit arrays.

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arXiv2026

Spacetime-Efficient and Hardware-Compatible Complex Quantum Logic Units in qLDPC Codes

Quantum low-density parity-check (qLDPC) codes offer a promising route to scalable fault-tolerant quantum computing due to their substantially reduced footprint. However, these gains can be diluted at utility scale if we cannot also realize space-time efficient logical operations for relevant quantum applications. We present RASCqL, a reaction-time-limited architecture for space-time efficient complex-instruction-set quantum computation with qLDPC logic. RASCqL supports key algorithmic subroutines such as quantum arithmetic and state preparation directly within co-designed qLDPC codes, achieving $2\times$ to $7\times$ reductions in qubit footprint while maintaining space-time volume comparable to state-of-the-art transversal surface-code architectures. Unlike prior approaches that aim for versatile logical instruction sets for arbitrary circuits, RASCqL adopts an application-tailored code modification that embeds specific complex Clifford transformations useful for common subroutines as virtually implementable operations arising from code automorphisms. RASCqL further leverages parallel physical operations available in reconfigurable neutral-atom arrays to enable fast QEC cycles and high-fidelity transversal operations. At the cost of increased design complexity and specialization, RASCqL can improve end-to-end resource estimates for applications such as factoring and quantum chemistry simulation in both footprint and space-time volume under realistic physical error rates of approximately $2\times10^{-3}$ to $5\times10^{-4}$, without requiring additional hardware capabilities. These results demonstrate that qLDPC codes can serve as complex quantum logic units for useful quantum algorithms, extending their practical utility in fault-tolerant quantum computing architectures.

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arXiv2026

PropHunt: Automated Optimization of Quantum Syndrome Measurement Circuits

Fault-Tolerant Quantum Computing (FTQC) relies on Quantum Error Correction (QEC) codes to reach error rates necessary for large scale quantum applications. At a physical level, QEC codes perform parity checks on data qubits, producing syndrome information, through Syndrome Measurement (SM) circuits. These circuits define a code's logical error rate and must be run repeatedly throughout the entire program. The performance of SM circuits is therefore critical to the success of a FTQC system. While ultimately implemented as physical circuits, SM circuits have challenges that are not addressed by existing circuit optimization tools. Importantly, inside SM circuits themselves errors are expected to occur, and how errors propagate through SM circuits directly impacts which errors are detectable and correctable, defining the code's logical error rate. This is not modeled in NISQ-era tools, which instead optimize for targets such as gate depth or gate count to mitigate the chance that any error occurs. This gap leaves key questions unanswered about the expected real-world effectiveness of QEC codes. In this work we address this gap and present PropHunt, an automated tool for optimizing SM circuits for CSS codes. We evaluate PropHunt on a suite of relevant QEC codes and demonstrate PropHunt's ability to iteratively improve performance and recover existing hand-designed circuits automatically. We also propose a near-term QEC application, Hook-ZNE, which leverages PropHunt's fine-grained control over logical error rate to improve Zero-Noise Extrapolation (ZNE), a promising error mitigation strategy.

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arXiv2025

Erasure Minesweeper: exploring hybrid-erasure surface code architectures for efficient quantum error correction

Dual-rail erasure qubits can substantially improve the efficiency of quantum error correction, allowing lower error rates to be achieved with fewer qubits, but each erasure qubit requires $3\times$ more transmons to implement compared to standard qubits. In this work, we introduce a hybrid-erasure architecture for surface code error correction where a carefully chosen subset of qubits is designated as erasure qubits while the rest remain standard. Through code-capacity analysis and circuit-level simulations, we show that a hybrid-erasure architecture can boost the performance of the surface code -- much like how a game of Minesweeper becomes easier once a few squares are revealed -- while using fewer resources than a full-erasure architecture. We study strategies for the allocation and placement of erasure qubits through analysis and simulations. We then use the hybrid-erasure architecture to explore the trade-offs between per-qubit cost and key logical performance metrics such as threshold and effective distance in surface code error correction. Our results show that the strategic introduction of dual-rail erasure qubits in a transmon architecture can enhance the logical performance of surface codes for a fixed transmon budget, particularly for near-term-relevant transmon counts and logical error rates.

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arXiv2024

Predictive Window Decoding for Fault-Tolerant Quantum Programs

Real-time decoding is a key ingredient in future fault-tolerant quantum systems, yet many decoders are too slow to run in real time. Prior work has shown that parallel window decoding schemes can scalably meet throughput requirements in the presence of increasing decoding times, given enough classical resources. However, windowed decoding schemes require that some decoding tasks be delayed until others have completed, which can be problematic during time-sensitive operations such as T gate teleportation, leading to suboptimal program runtimes. To alleviate this, we introduce a speculative window decoding scheme. Taking inspiration from branch prediction in classical computer architecture our decoder utilizes a light-weight speculation step to predict data dependencies between adjacent decoding windows, allowing multiple layers of decoding tasks to be resolved simultaneously. Through a state-of-the-art compilation pipeline and a detailed simulator, we find that speculation reduces application runtimes by 40% on average compared to prior parallel window decoders.

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arXiv2024

Averting multi-qubit burst errors in surface code magic state factories

Fault-tolerant quantum computation relies on the assumption of time-invariant, sufficiently low physical error rates. However, current superconducting quantum computers suffer from frequent disruptive noise events, including cosmic ray impacts and shifting two-level system defects. Several methods have been proposed to mitigate these issues in software, but they add large overheads in terms of physical qubit count, as it is difficult to preserve logical information through burst error events. We focus on mitigating multi-qubit burst errors in magic state factories, which are expected to comprise up to 95% of the space cost of future quantum programs. Our key insight is that magic state factories do not need to preserve logical information over time; once we detect an increase in local physical error rates, we can simply turn off parts of the factory that are affected, re-map the factory to the new chip geometry, and continue operating. This is much more efficient than previous more general methods, and is resilient even under many simultaneous impact events. Using precise physical noise models, we show an efficient ray detection method and evaluate our strategy in different noise regimes. Compared to existing baselines, we find reductions in ray-induced overheads by several orders of magnitude, reducing total qubitcycle cost by geomean 6.5x to 13.9x depending on the noise model. This work reduces the burden on hardware by providing low-overhead software mitigation of these errors.

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arXiv2024

Codesign of quantum error-correcting codes and modular chiplets in the presence of defects

Fabrication errors pose a significant challenge in scaling up solid-state quantum devices to the sizes required for fault-tolerant (FT) quantum applications. To mitigate the resource overhead caused by fabrication errors, we combine two approaches: (1) leveraging the flexibility of a modular architecture, (2) adapting the procedure of quantum error correction (QEC) to account for fabrication defects. We simulate the surface code adapted to qubit arrays with arbitrarily distributed defects to find metrics that characterize how defects affect fidelity. We then determine the impact of defects on the resource overhead of realizing a fault-tolerant quantum computer, on a chiplet-based modular architecture. Our strategy for dealing with fabrication defects demonstrates an exponential suppression of logical failure where error rates of non-faulty physical qubits are ~0.1% in a circuit-based noise model. This is a typical regime where we imagine running the defect-free surface code. We use our numerical results to establish post-selection criteria for building a device from defective chiplets. Using our criteria, we then evaluate the resource overhead in terms of the average number of fabricated physical qubits per logical qubit. We find that an optimal choice of chiplet size, based on the defect rate and target fidelity, is essential to limiting any additional error correction overhead due to defects. When the optimal chiplet size is chosen, at a defect rate of 1% the resource overhead can be reduced to below 3X and 6X respectively for the two defect models we use, for a wide range of target performance. We also determine cutoff fidelity values that help identify whether a qubit should be disabled or kept as part of the error correction code.

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arXiv2023

An Architecture for Improved Surface Code Connectivity in Neutral Atoms

In order to achieve error rates necessary for advantageous quantum algorithms, Quantum Error Correction (QEC) will need to be employed, improving logical qubit fidelity beyond what can be achieved physically. As today's devices begin to scale, co-designing architectures for QEC with the underlying hardware will be necessary to reduce the daunting overheads and accelerate the realization of practical quantum computing. In this work, we focus on logical computation in QEC. We address quantum computers made from neutral atom arrays to design a surface code architecture that translates the hardware's higher physical connectivity into a higher logical connectivity. We propose groups of interleaved logical qubits, gaining all-to-all connectivity within the group via efficient transversal CNOT gates. Compared to standard lattice surgery operations, this reduces both the overall qubit footprint and execution time, lowering the spacetime overhead needed for small-scale QEC circuits. We also explore the architecture's scalability. We look at using physical atom movement schemes and propose interleaved lattice surgery which allows an all-to-all connectivity between qubits in adjacent interleaved groups, creating a higher connectivity routing space for large-scale circuits. Using numerical simulations, we evaluate the total routing time of interleaved lattice surgery and atom movement for various circuit sizes. We identify a cross-over point defining intermediate-scale circuits where atom movement is best and large-scale circuits where interleaved lattice surgery is best. We use this to motivate a hybrid approach as devices continue to scale, with the choice of operation depending on the routing distance.

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arXiv2023

Training Quantum Boltzmann Machines with Coresets

Recent work has proposed and explored using coreset techniques for quantum algorithms that operate on classical data sets to accelerate the applicability of these algorithms on near-term quantum devices. We apply these ideas to Quantum Boltzmann Machines (QBM) where gradient-based steps which require Gibbs state sampling are the main computational bottleneck during training. By using a coreset in place of the full data set, we try to minimize the number of steps needed and accelerate the overall training time. In a regime where computational time on quantum computers is a precious resource, we propose this might lead to substantial practical savings. We evaluate this approach on 6x6 binary images from an augmented bars and stripes data set using a QBM with 36 visible units and 8 hidden units. Using an Inception score inspired metric, we compare QBM training times with and without using coresets.

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arXiv2022

Fast Fingerprinting of Cloud-based NISQ Quantum Computers

Cloud-based quantum computers have become a reality with a number of companies allowing for cloud-based access to their machines with tens to more than 100 qubits. With easy access to quantum computers, quantum information processing will potentially revolutionize computation, and superconducting transmon-based quantum computers are among some of the more promising devices available. Cloud service providers today host a variety of these and other prototype quantum computers with highly diverse device properties, sizes, and performances. The variation that exists in today's quantum computers, even among those of the same underlying hardware, motivate the study of how one device can be clearly differentiated and identified from the next. As a case study, this work focuses on the properties of 25 IBM superconducting, fixed-frequency transmon-based quantum computers that range in age from a few months to approximately 2.5 years. Through the analysis of current and historical quantum computer calibration data, this work uncovers key features within the machines that can serve as basis for unique hardware fingerprint of each quantum computer. This work demonstrates a new and fast method to reliably fingerprint cloud-based quantum computers based on unique frequency characteristics of transmon qubits. Both enrollment and recall operations are very fast as fingerprint data can be generated with minimal executions on the quantum machine. The qubit frequency-based fingerprints also have excellent inter-device separation and intra-device stability.

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arXiv2022

SupermarQ: A Scalable Quantum Benchmark Suite

The emergence of quantum computers as a new computational paradigm has been accompanied by speculation concerning the scope and timeline of their anticipated revolutionary changes. While quantum computing is still in its infancy, the variety of different architectures used to implement quantum computations make it difficult to reliably measure and compare performance. This problem motivates our introduction of SupermarQ, a scalable, hardware-agnostic quantum benchmark suite which uses application-level metrics to measure performance. SupermarQ is the first attempt to systematically apply techniques from classical benchmarking methodology to the quantum domain. We define a set of feature vectors to quantify coverage, select applications from a variety of domains to ensure the suite is representative of real workloads, and collect benchmark results from the IBM, IonQ, and AQT@LBNL platforms. Looking forward, we envision that quantum benchmarking will encompass a large cross-community effort built on open source, constantly evolving benchmark suites. We introduce SupermarQ as an important step in this direction.

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arXiv2021

Adapting Quantum Approximation Optimization Algorithm (QAOA) for Unit Commitment

In the present Noisy Intermediate-Scale Quantum (NISQ), hybrid algorithms that leverage classical resources to reduce quantum costs are particularly appealing. We formulate and apply such a hybrid quantum-classical algorithm to a power system optimization problem called Unit Commitment, which aims to satisfy a target power load at minimal cost. Our algorithm extends the Quantum Approximation Optimization Algorithm (QAOA) with a classical minimizer in order to support mixed binary optimization. Using Qiskit, we simulate results for sample systems to validate the effectiveness of our approach. We also compare to purely classical methods. Our results indicate that classical solvers are effective for our simulated Unit Commitment instances with fewer than 400 power generation units. However, for larger problem instances, the classical solvers either scale exponentially in runtime or must resort to coarse approximations. Potential quantum advantage would require problem instances at this scale, with several hundred units.

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