arXiv subjects

Juan P. Mendez

Publications and source records attributed to Juan P. Mendez.

12 recordsLinked to original sources

arXiv2026

Revealing New Leakage Paths in GAAFETs using Predictive First-Principles Simulations

Gate-All-Around Field-Effect Transistors (GAAFETs) are emerging as successors to Fin Field-Effect Transistors (FinFETs) and are central to continued scaling at advanced semiconductor nodes. Despite their improved electrostatic control, recent measurements show that the drain current in GAAFETs deviates strongly from thermionic behavior at negative gate voltages, increasing as the gate voltage becomes more negative. This leakage has been attributed to direct gate-drain tunneling through the high-$k$ dielectric, enhanced by drain-induced dielectric barrier lowering (DIDBL). Here, we use predictive, charge-self-consistent Non-Equilibrium Green Function (NEGF) simulations based on the Contact Block Reduction (CBR) method to spatially resolve this leakage pathway in GAAFETs. Unlike approaches based primarily on phenomenological leakage models, our first-principles, multi-terminal quantum-transport framework treats the source, drain, and gate as current-carrying quantum-mechanical contacts and resolves the local current density throughout the device. The spatially resolved current density shows that gate-injected carriers tunnel through the high-$k$ dielectric preferentially near the drain side of the gate, where the dielectric barrier is most strongly lowered by the drain bias, and are collected by the drain. This provides a direct real-space picture of the DIDBL-driven gate-drain leakage mechanism.

cond-mat.other↗

arXiv2026

JFS-CryoMem: A Cryogenic Memory with Voltage-Controlled Superconducting Devices and Femtojoule-Scale Write/Read Energies

Scalable cryogenic systems require memory that combines nonvolatile storage, selective access, low thermal disturbance, and compatibility with superconducting electronics. We present a cryogenic memory architecture that integrates a voltage-controlled Josephson junction field-effect transistor (JJFET) selector with a ferroelectric superconducting quantum interference device (FeSQUID) storage element, hereafter termed JFS-CryoMem. The JJFET provides gate-controlled cell selection, whereas the FeSQUID stores information in stable remanent-polarization states. JFS-CryoMem features separate read and write path mechanisms that support nondestructive readout and independent optimization of programming and sensing conditions. The architecture is evaluated using experimentally calibrated compact models that reproduce the measured electrical characteristics of both constituent devices. We demonstrate selective programming using a half-bias scheme, nonvolatile state retention, and distinguishable readout in a $4 \times 4$ array while accounting for the selected cell and all unselected parallel branches. We then extend the analysis to arrays up to $16 \times 16$ and examine how array scaling alters current distribution, column-equivalent resistance, readout separation, required bitline current, and read energy. The results reveal the principal sensing and energy tradeoffs associated with larger arrays and identify the operating conditions required to preserve read distinguishability as the array grows. JFS-CryoMem provides a device-to-array framework for cryogenic memory in quantum, high-performance, and space-oriented computing systems.

cs.ET↗

arXiv2026

Predictive first-principles simulations for co-designing next-generation energy-efficient AI systems

In modern generative-AI workloads, matrix-vector/matrix-matrix multiplications (\emph{MatMul}) dominate the compute and energy cost. Achieving dramatic reductions in energy per token therefore requires a novel, specialized hardware that is co-designed across materials, devices, interconnects, circuits, and architectures rather than optimized at any single layer in isolation. In this \emph{Perspectives} article, we argue that \emph{predictive} (first-principles, fitting-parameter-free) device and interconnect simulations can close the loop between nanoscale physics and workload-level metrics, enabling the identification of device/interconnect operating regimes that plausibly support \emph{orders-of-magnitude} improvements in energy efficiency of AI accelerators.

cond-mat.other↗

arXiv2026

Gate-Drain Leakage Enhanced by Drain-Induced Dielectric Barrier Lowering in Gate-All-Around Field Effect Transistors

Gate-All-Around Field-Effect Transistors (GAAFETs), now entering high-volume production as successors to fin field-effect transistor technology, are enabling continued scaling and enhanced performance in advanced semiconductor nodes. However, the drain-current in GAAFETs strongly deviates from the thermionic dependence at negative gate voltages, exhibiting the existence of leakage that is additionally enhanced at high applied biases. Understanding the origin of this leakage is essential for determining the scaling limits of GAAFETs and for guiding device and material optimizations aimed at suppressing the off-state current. Additionally, recent experimental measurements have revealed the increased influence of radiation-induced defects in the negative gate voltage regime, with their impact remaining largely negligible for positive gate voltages. Through predictive first-principles simulations, we demonstrate that the observed leakage current at negative gate voltages originates from gate-to-drain tunneling, which is significantly enhanced by drain-induced dielectric barrier lowering between the gate and drain.

cond-mat.other↗

arXiv2025

Analog-to-Digital Converter Based on Voltage-controlled Superconducting Device

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra energy efficient data conversion architectures that remain functional at deep cryogenic temperatures.In this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a novel quantum enhanced Josephson junction field effect transistor (JJFET).Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current controlled superconducting devices while aligning naturally with CMOS style design methodologies.Building on our previously developed Verilog A compact model calibrated to experimental data, we design and simulate a three bit JJFET based flash ADC.The core comparator block is realized through careful bias current selection and augmented with a three terminal nanocryotron to precisely define reference voltages.Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic level restoration across stages.Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage driven superconducting mixed signal circuits.This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum classical co-processors, low-power AI accelerators, and next generation energy constrained computing platforms.

cond-mat.supr-con↗

arXiv2025

Reimagining Voltage-Controlled Cryogenic Boolean Logic Paradigm with Quantum-Enhanced Josephson Junction FETs

The growing demand for ultra low power computing and the emergence of quantum technologies have intensified interest in cryogenic electronics, particularly superconducting devices. Despite their promise, current controlled superconducting components face fundamental challenges in cascadability, limiting their effectiveness in complex logic architectures. To overcome this, recent efforts have focused on developing gate tunable superconducting devices, such as Josephson junction field effect transistors (JJFETs). However, achieving robust control and sufficient supercurrent gain, both critical for transistor-like performance in logic circuits remains a key challenge. A recent advancement in JJFET design, based on InAs and GaSb heterostructures, demonstrates enhanced gain and favorable device characteristics suitable for circuit integration. Building on this innovation, we propose and analyze fundamental voltage controlled logic topologies using the quantum enhanced JJFET. We develop a Verilog A based circuit compatible compact model of the quantum enhanced JJFET which accurately captures the experimentally observed device characteristics. To ensure cascadability, our logic circuits incorporate the multilayered Heater Nanocryotron (nTron), a superconducting nanowire-based thermal switch. Through simulation based analysis, we demonstrate the successful implementation of fundamental logic gates, including NOT, NAND, and NOR. Furthermore, we design a 3 input majority gate, which plays a pivotal role in quantum and reversible computing due to its universality. Finally, to demonstrate the cascadability of our proposed logic topology, we demonstrate the operation of a 2 input XOR gate based on our designed JJFET based NOT, NAND, and NOR gate.

cs.ET↗

arXiv2025

Quantum charge sensing using a semiconductor device based on $δ$-layer tunnel junctions

We report a nanoscale device concept based on a highly doped $δ$-layer tunnel junction embedded in a semiconductor for charge sensing. Recent advances in Atomic Precision Advanced Manufacturing (APAM) processes have enabled the fabrication of devices based on quasi-2D, highly conductive, highly doped regions, known as $δ$-layers, in semiconductor materials. In this work, we demonstrate that APAM $δ$-layer tunnel junctions are ultrasensitive to the presence of charges near the tunnel junction, allowing the use of these devices for detecting charges by observing changes in the electrical current. We demonstrate that these devices can enhance the sensitivity in the limit, i.e., for small concentrations of charges, exhibiting significantly superior sensitivity compared to traditional FET-based sensors. We also propose that the extreme sensitivity arises from the strong quantization of the conduction band in these highly-confined systems.

cond-mat.mes-hall↗

arXiv2025

Exploring transport mechanisms in atomic precision advanced manufacturing enabled pn junctions

We investigate the different transport mechanisms that can occur in pn junction devices made using atomic precision advanced manufacturing (APAM) at temperatures ranging from cryogenic to room temperature. We first elucidate the potential cause of the anomalous behavior observed in the forward-bias response of these devices in recent cryogenic temperature measurements, which deviates from the theoretical response of a silicon Esaki diode. These anomalous behaviors include current suppression at low voltages in the forward-bias response and a much lower valley voltage at cryogenic temperatures than theoretically expected for a silicon diode. To investigate the potential causes of these anomalies, we studied the effects of a few possible transport mechanisms, including band-to-band tunneling, band gap narrowing, potential impact of non-Ohmic contacts, band quantization, impact of leakage, and inelastic trap-assisted tunneling, through semi-classical simulations. We find that a combination of two sets of band-to-band tunneling (BTBT) parameters can qualitatively approximate the shape of the tunneling current at low bias. This can arise from band quantization and realignment due to the strong potential confinement in $δ$-layers. We also find that the lower-than-theoretically-expected valley voltage can be attributed to modifications in the electronic band structure within the $δ$-layer regions, leading to a significant band-gap narrowing induced by the high density of dopants. Finally, we extend our analyses to room temperature operation and predict that trap-assisted tunneling (TAT) facilitated by phonon interactions may become significant, leading to a complex superposition of BTBT and TAT transport mechanisms in the electrical measurements.

cond-mat.mes-hall↗

arXiv2023

Uncovering anisotropic effects of electric high-moment dipoles on the tunneling current in $δ$-layer tunnel junctions

The precise positioning of dopants in semiconductors using scanning tunneling microscopes has led to the development of planar dopant-based devices, also known as $δ$-layers, facilitating the exploration of new concepts in classical and quantum computing. Recently it have been shown that two distinct conductivity regimes (low- and high- bias regimes) exist in $δ$-layer tunnel junctions due to the presence of quasi-discrete and continuous states in the conduction band of $δ$-layer systems. Furthermore, discrete charged impurities in the tunnel junction region significantly influence the tunneling rates in $δ$-layer tunnel junctions. Here we demonstrate that zero-charge impurities, or electrical dipoles, present in the tunnel junction region can also significantly alter the tunneling rate, depending, however, on the specific conductivity regime and orientation and moment of the dipole. In the low-bias regime with high-resistance tunneling mode dipole impurities of nearly all orientations and moments can alter the current, indicating the extreme sensitivity of the tunnel current to the slightest imperfection in the tunnel gap. In the high-bias regime with low-resistivity only dipole defects with high moment and orientated in the direction perpendicular to the electron tunneling direction can significantly affect the current, thus making this conductivity regime significantly less prone to the influence of dipole defects with low-moment or dipoles oriented along the propagation direction.

cond-mat.mes-hall↗

arXiv2023

Influence of imperfections on tunneling rate in $δ$-layer junctions

The atomically precise placement of dopants in semiconductors using scanning tunneling microscopes has been used to create planar dopant-based devices, enabling the exploration of novel classical or quantum computing concepts, which often require precise control over tunneling rates in their operation. While the geometry of the dopants can be defined to sub-nanometer precision, imperfections can still play a significant role in determining the tunneling rates. Here, we investigate the influence of different imperfections in phosphorous $δ$-layer tunnel junctions in silicon: variations of $δ$-layer thickness and tunnel gap width, interface roughness, and charged impurities. It is found that while most of the imperfections moderately affect the tunneling rate, a single charged impurity in the tunnel gap can alter the tunneling rate by more than an order of magnitude, even for relatively large tunnel gaps. Moreover, it is also revealed that the tunneling rate strongly depends on the electrical charge sign of the impurity.

cond-mat.mes-hall↗

arXiv2022

Strong Quantization of Current-carrying Electron States in $δ$-layer Systems

We present an open-system quantum-mechanical real-space study of the conductive properties and size quantization in phosphorus $δ$-layers systems, interesting for their beyond-Moore and quantum computing applications. Recently it has been demonstrated that an open-system quantum mechanical treatment provides a much more accurate match to ARPES measurements in highly-conductive, highly-confined systems than the traditional approaches (i.e. periodic or Dirichlet boundary conditions) and, furthermore, it allows accurate predictions of conductive properties of such systems from the first principles. Here we reveal that quantization effects are strong for device widths $W<10$~nm, and we show, for the first time, that the number of propagating modes determines not only the conductivity, but the distinctive spatial distribution of the current-carrying electron states. For $W>10$~nm, the quantization effects practically vanish and the conductivity tends to the infinitely-wide device's values.

cond-mat.mes-hall↗

arXiv2022

Conductivity and size quantization effects in semiconductor $δ$-layer systems

We present an open-system quantum-mechanical 3D real-space study of the conduction band structure and conductive properties of two semiconductor systems, interesting for their beyond-Moore and quantum computing applications: phosphorus $δ$-layers in silicon and the corresponding $δ$-layer tunnel junctions. In order to evaluate size quantization effects on the conductivity, we consider two principal cases: nanoscale finite-width structures, used in transistors, and infinitely-wide structures, electrical properties of which are typically known experimentally. For devices widths $W<10$~nm, quantization effects are strong and it is shown that the number of propagating modes determines not only the conductivity, but the distinctive spatial distribution of the current-carrying electron states. For $W>10$~nm, the quantization effects practically vanish and the conductivity tends to the infinitely-wide device values. For tunnel junctions, two distinct conductivity regimes are predicted due to the strong conduction band quantization.

cond-mat.mes-hall↗