Junbin Long | Searcharxiv

arXiv2026

SimAMC: A Fast and Accurate Simulator for Resistive Memory-Based Analog Matrix Computing with Non-Idealities

Analog matrix computing (AMC) circuits leverage resistive memory arrays to perform matrix operations in a massively parallel manner, providing an efficient approach for accelerating data-intensive tasks. However, hardware non-idealities severely impact computational accuracy, making early-stage simulation vital for reliable performance estimation and design optimization. While open-loop circuits for matrix-vector multiplication are well-studied, closed-loop AMC circuits, which solve matrix equations, are computationally more complex and substantially more sensitive to non-idealities, complicating their simulation. In this work, we present SimAMC, a simulator for resistive memory-based closed-loop AMC circuits. SimAMC is capable of modeling matrix inversion and eigenvector solving in the presence of key non-idealities, including device programming error, data conversion error, thermal noise, operational amplifier input offset, and interconnect resistance. For real-valued matrix computing circuits, an alternating iterative algorithm is designed. SimAMC's effectiveness is validated through comparison with SPICE, showing excellent agreement while also demonstrating a speedup of several orders of magnitude.

cs.ET↗

arXiv2025

Modeling Closed-loop Analog Matrix Computing Circuits with Interconnect Resistance

Analog matrix computing (AMC) circuits based on resistive random-access memory (RRAM) have shown strong potential for accelerating matrix operations. However, as matrix size grows, interconnect resistance increasingly degrades computational accuracy and limits circuit scalability. Modeling and evaluating these effects are therefore critical for developing effective mitigation strategies. Traditional SPICE (Simulation Program with Integrated Circuit Emphasis) simulators, which rely on modified nodal analysis, become prohibitively slow for large-scale AMC circuits due to the quadratic growth of nodes and feedback connections. In this work, we model AMC circuits with interconnect resistance for two key operations-matrix inversion (INV) and eigenvector computation (EGV), and propose fast solving algorithms tailored for each case. The algorithms exploit the sparsity of the Jacobian matrix, enabling rapid and accurate solutions. Compared to SPICE, they achieve several orders of magnitude acceleration while maintaining high accuracy. We further extend the approach to open-loop matrix-vector multiplication (MVM) circuits, demonstrating similar efficiency gains. Finally, leveraging these fast solvers, we develop a bias-based compensation strategy that reduces interconnect-induced errors by over 50% for INV and 70% for EGV circuits. It also reveals the scaling behavior of the optimal bias with respect to matrix size and interconnect resistance.

cs.ET↗