arXiv subjects

Junsong Wang

Publications and source records attributed to Junsong Wang.

20 records · Page 2Linked to original sources

arXiv2020

Polar Rectification Effect in Electro-Fatigued SrTiO3 Based Junctions

Rectifying semiconductor junctions are crucial to electronic devices. They convert alternating current into direct one by allowing unidirectional charge flows. In analogy to the current-flow rectification for itinerary electrons, here, a polar rectification that based on the localized oxygen vacancies (OVs) in a Ti/fatigued-SrTiO3 (fSTO) Schottky junction is first demonstrated. The fSTO with OVs is produced by an electro-degradation process. The different movability of localized OVs and itinerary electrons in the fSTO yield a unidirectional electric polarization at the interface of the junction under the coaction of external and built-in electric fields. Moreover, the fSTO displays a pre-ferroelectric state located between paraelectric and ferroelectric phases. The pre-ferroelectric state has three sub-states and can be easily driven into a ferroelectric state by external electric field. These observations open up opportunities for potential polar devices and may underpin many useful polar-triggered electronic phenomena.

physics.app-ph↗

arXiv2018

Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA

Neural network accelerators with low latency and low energy consumption are desirable for edge computing. To create such accelerators, we propose a design flow for accelerating the extremely low bit-width neural network (ELB-NN) in embedded FPGAs with hybrid quantization schemes. This flow covers both network training and FPGA-based network deployment, which facilitates the design space exploration and simplifies the tradeoff between network accuracy and computation efficiency. Using this flow helps hardware designers to deliver a network accelerator in edge devices under strict resource and power constraints. We present the proposed flow by supporting hybrid ELB settings within a neural network. Results show that our design can deliver very high performance peaking at 10.3 TOPS and classify up to 325.3 image/s/watt while running large-scale neural networks for less than 5W using embedded FPGA. To the best of our knowledge, it is the most energy efficient solution in comparison to GPU or other FPGA implementations reported so far in the literature.

cs.DC↗