arXiv subjects

Katayoon Yahyaei

Publications and source records attributed to Katayoon Yahyaei.

3 recordsLinked to original sources

arXiv2026

AI-Driven Thermal Mapping and Management in 3D Integrated Photonic Circuits

Photonic Integrated Circuits (PICs) are advancing high-performance computing, data centers, and sensing, yet three-dimensional (3D) PICs introduce critical thermal management challenges due to high-density bonding and heterogeneous materials. Traditional methods like thermal microscopes and in-package sensors yield sparse data, limiting full thermal profile visibility. This paper presents a dual-method solution combining an AI-driven thermal modeling framework with a design-based heuristic approach. The AI method integrates sparse sensor data with design layer and density information to predict multilayer temperature variations, while the heuristic approach uses localized material properties, design layout, component geometries, and sensor coordinates to refine thermal estimations in specific regions. A 2D thermal map of a 3D PIC is generated by interpolating sensor data and adjusting for local thermal resistivity using comparative analysis between design regions. The heuristic method complements the AI model, improving estimation accuracy without extensive training data. Together, these methods offer a scalable, accurate solution for real-time thermal mapping and design-time simulation, enabling reliable thermal management in next-generation 3D photonic systems.

cs.AR↗

arXiv2026

Design Guidelines for In-line X-ray Inspection in Advanced Packaging Technology: A CoWoS Case Study

The shift towards advanced packaging technologies, including 2.5D and 3D integration, addresses the limitations of traditional methods while meeting increasing demands for performance, miniaturization, and efficiency. These methods enhance functionality and support heterogeneous integration but also introduce metrology challenges due to complex, three-dimensional structures. X-ray imaging, crucial for nondestructive inspection, faces compatibility issues such as material density similarities and noise scattering. To address these challenges, we propose a framework based on AI-integrated Design of Experiment (DoE) to develop design guidelines to optimize X-ray compatibility during the design stage. This framework, demonstrated through a case study on Chip-on-Wafer-on-Substrate (CoWoS) packaging, systematically analyzes design parameters and material properties to develop guidelines for improved inspection accuracy. Our method integrates AI to predict outcomes and optimize processes, ensuring high-quality X-ray images and enhancing defect detection. Implementing these guidelines can significantly improve inspection accuracy and reliability, reducing production costs and supporting the efficiency and scalability of advanced semiconductor technologies.

eess.IV↗

arXiv2023

LLM for SoC Security: A Paradigm Shift

As the ubiquity and complexity of system-on-chip (SoC) designs increase across electronic devices, the task of incorporating security into an SoC design flow poses significant challenges. Existing security solutions are inadequate to provide effective verification of modern SoC designs due to their limitations in scalability, comprehensiveness, and adaptability. On the other hand, Large Language Models (LLMs) are celebrated for their remarkable success in natural language understanding, advanced reasoning, and program synthesis tasks. Recognizing an opportunity, our research delves into leveraging the emergent capabilities of Generative Pre-trained Transformers (GPTs) to address the existing gaps in SoC security, aiming for a more efficient, scalable, and adaptable methodology. By integrating LLMs into the SoC security verification paradigm, we open a new frontier of possibilities and challenges to ensure the security of increasingly complex SoCs. This paper offers an in-depth analysis of existing works, showcases practical case studies, demonstrates comprehensive experiments, and provides useful promoting guidelines. We also present the achievements, prospects, and challenges of employing LLM in different SoC security verification tasks.

cs.CR↗