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Kaushal Mhapsekar

Publications and source records attributed to Kaushal Mhapsekar.

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CacheMind: From Miss Rates to Why -- Natural-Language, Trace-Grounded Reasoning for Cache Replacement

Cache replacement remains a challenging problem in CPU microarchitecture, often addressed using hand-crafted heuristics, limiting cache performance. Cache data analysis requires parsing millions of trace entries with manual filtering, making the process slow and non-interactive. To address this, we introduce CacheMind, a conversational tool that uses Retrieval-Augmented Generation (RAG) and Large Language Models (LLMs) to enable semantic reasoning over cache traces. Architects can now ask natural language questions like, "Why is the memory access associated with PC X causing more evictions?", and receive trace-grounded, human-readable answers linked to program semantics for the first time. To evaluate CacheMind, we present CacheMindBench, the first verified benchmark suite for LLM-based reasoning for the cache replacement problem. Using the SIEVE retriever, CacheMind achieves 66.67% on 75 unseen trace-grounded questions and 84.80% on 25 unseen policy-specific reasoning tasks; with RANGER, it achieves 89.33% and 64.80% on the same evaluations. Additionally, with RANGER, CacheMind achieves 100% accuracy on 4 out of 6 categories in the trace-grounded tier of CacheMindBench. Compared to LlamaIndex (10% retrieval success), SIEVE achieves 60% and RANGER achieves 90%, demonstrating that existing Retrieval-Augmented Generation (RAGs) are insufficient for precise, trace-grounded microarchitectural reasoning. We provided four concrete actionable insights derived using CacheMind, wherein bypassing use case improved cache hit rate by 7.66% and speedup by 2.04%, software fix use case gives speedup of 76%, and Mockingjay replacement policy use case gives speedup of 0.7%; showing the utility of CacheMind on non-trivial queries that require a natural-language interface.

cs.AR

EdgeP4: A P4-Programmable Edge Intelligent Ethernet Switch for Tactile Cyber-Physical Systems

Tactile Internet based operations, e.g., telesurgery, rely on end-to-end closed loop control for accuracy and corrections. The feedback and control are subject to network latency and loss. We design two edge intelligence algorithms hosted at P4 programmable end switches. These algorithms locally compute and command corrective signals, thereby dispense the feedback signals from traversing the network to the other ends and save on control loop latency and network load. We implement these algorithms entirely on data plane on Netronome Agilio SmartNICs using P4. Our first algorithm, $\textit{pose correction}$, is placed at the edge switch connected to an industrial robot gripping a tool. The round trip between transmitting force sensor array readings to the edge switch and receiving correct tip coordinates at the robot is shown to be less than $100~μs$. The second algorithm, $\textit{tremor suppression}$, is placed at the edge switch connected to the human operator. It suppresses physiological tremors of amplitudes smaller than $100~μm$ which not only improves the application's performance but also reduces the network load up to $99.9\%$. Our solution allows edge intelligence modules to seamlessly switch between the algorithms based on the tasks being executed at the end hosts.

cs.NI