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Kaushik Roy

Publications and source records attributed to Kaushik Roy.

At least 289 records · Page 16Linked to original sources
arXiv2016

Ising spin model using Spin-Hall Effect (SHE) induced magnetization reversal in Magnetic-Tunnel-Junction

Ising spin model is considered as an efficient computing method to solve combinatorial optimization problems based on its natural tendency of convergence towards low energy state. The underlying basic functions facilitating the Ising model can be categorized into two parts, "Annealing and Majority vote". In this paper, we propose an Ising cell based on Spin Hall Effect (SHE) induced magnetization switching in a Magnetic Tunnel Junction (MTJ). The stochasticity of our proposed Ising cell based on SHE induced MTJ switching, can implement the natural annealing process by preventing the system from being stuck in solutions with local minima. Further, by controlling the current through the Heavy-Metal (HM) underlying the MTJ, we can mimic the majority vote function which determines the next state of the individual spins. By solving coupled \textit{Landau-Lifshitz-Gilbert} (LLG) equations, we demonstrate that our Ising cell can be replicated to map certain combinatorial problems. We present results for two representative problems - Maximum-cut and Graph coloring - to illustrate the feasibility of the proposed device-circuit configuration in solving combinatorial problems. Our proposed solution using a Heavy Metal (HM) based MTJ device can be exploited to implement compact, fast, and energy efficient Ising spin model.

cs.ET↗
arXiv2016

Energy-Efficient Object Detection using Semantic Decomposition

Machine-learning algorithms offer immense possibilities in the development of several cognitive applications. In fact, large scale machine-learning classifiers now represent the state-of-the-art in a wide range of object detection/classification problems. However, the network complexities of large-scale classifiers present them as one of the most challenging and energy intensive workloads across the computing spectrum. In this paper, we present a new approach to optimize energy efficiency of object detection tasks using semantic decomposition to build a hierarchical classification framework. We observe that certain semantic information like color/texture are common across various images in real-world datasets for object detection applications. We exploit these common semantic features to distinguish the objects of interest from the remaining inputs (non-objects of interest) in a dataset at a lower computational effort. We propose a 2-stage hierarchical classification framework, with increasing levels of complexity, wherein the first stage is trained to recognize the broad representative semantic features relevant to the object of interest. The first stage rejects the input instances that do not have the representative features and passes only the relevant instances to the second stage. Our methodology thus allows us to reject certain information at lower complexity and utilize the full computational effort of a network only on a smaller fraction of inputs to perform detection. We use color and texture as distinctive traits to carry out several experiments for object detection. Our experiments on the Caltech101/CIFAR10 dataset show that the proposed method yields 1.93x/1.46x improvement in average energy, respectively, over the traditional single classifier model.

cs.CV↗
arXiv2016

Investigation of Dependence between Time-zero and Time-dependent Variability in High-k NMOS Transistors

Bias Temperature Instability (BTI) is a major reliability concern in CMOS technology, especially with High dielectric constant (High-\k{appa}/HK) metal gate (MG) transistors. In addition, the time independent process induced variation has also increased because of the aggressive scaling down of devices. As a result, the faster devices at the lower threshold voltage distribution tail experience higher stress, leading to additional skewness in the BTI degradation. Since time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it is necessary to investigate the effect of time zero variability on all these effects simultaneously. To that effect, we propose a simulation framework to model and analyze the impact of time-zero variability (in particular, random dopant fluctuations) on different aging effects. For small area devices (~1000 nm2) in 30nm technology, we observe significant effect of Random Dopant Fluctuation (RDF) on BTI induced variability (σΔVth). In addition, the circuit analysis reveals similar trend on the performance degradation. However, both TDDB and SILC show weak dependence on RDF. We conclude that the effect of RDF on Vth degradation cannot be disregarded in scaled technology and needs to be considered for variation tolerant circuit design.

cond-mat.mes-hall↗
arXiv2016

Attention Tree: Learning Hierarchies of Visual Features for Large-Scale Image Recognition

One of the key challenges in machine learning is to design a computationally efficient multi-class classifier while maintaining the output accuracy and performance. In this paper, we present a tree-based classifier: Attention Tree (ATree) for large-scale image classification that uses recursive Adaboost training to construct a visual attention hierarchy. The proposed attention model is inspired from the biological 'selective tuning mechanism for cortical visual processing'. We exploit the inherent feature similarity across images in datasets to identify the input variability and use recursive optimization procedure, to determine data partitioning at each node, thereby, learning the attention hierarchy. A set of binary classifiers is organized on top of the learnt hierarchy to minimize the overall test-time complexity. The attention model maximizes the margins for the binary classifiers for optimal decision boundary modelling, leading to better performance at minimal complexity. The proposed framework has been evaluated on both Caltech-256 and SUN datasets and achieves accuracy improvement over state-of-the-art tree-based methods at significantly lower computational cost.

cs.CV↗
arXiv2016

Yield, Area and Energy Optimization in Stt-MRAMs using failure aware ECC

Spin Transfer Torque MRAMs are attractive due to their non-volatility, high density and zero leakage. However, STT-MRAMs suffer from poor reliability due to shared read and write paths. Additionally, conflicting requirements for data retention and write-ability (both related to the energy barrier height of the magnet) makes design more challenging. Furthermore, the energy barrier height depends on the physical dimensions of the free layer. Any variations in the dimensions of the free layer lead to variations in the energy barrier height. In order to address poor reliability of STT-MRAMs, usage of Error Correcting Codes (ECC) have been proposed. Unlike traditional CMOS memory technologies, ECC is expected to correct both soft and hard errors in STT_MRAMs. To achieve acceptable yield with low write power, stronger ECC is required, resulting in increased number of encoded bits and degraded memory efficiency. In this paper, we propose Failure aware ECC (FaECC), which masks permanent faults while maintaining the same correction capability for soft errors without increased encoded bits. Furthermore, we investigate the impact of process variations on run-time reliability of STT-MRAMs. We provide an analysis on the impact of process variations on the life-time of the free layer and retention failures. In order to analyze the effectiveness of our methodology, we developed a cross-layer simulation framework that consists of device, circuit and array level analysis of STT-MRAM memory arrays. Our results show that using FaECC relaxes the requirements on the energy barrier height, which reduces the write energy and results in smaller access transistor size and memory array area. Keywords: STT-MRAM, reliability, Error Correcting Codes, ECC, magnetic memory

cs.OH↗
arXiv2016

Probabilistic Deep Spiking Neural Systems Enabled by Magnetic Tunnel Junction

Deep Spiking Neural Networks are becoming increasingly powerful tools for cognitive computing platforms. However, most of the existing literature on such computing models are developed with limited insights on the underlying hardware implementation, resulting in area and power expensive designs. Although several neuromimetic devices emulating neural operations have been proposed recently, their functionality has been limited to very simple neural models that may prove to be inefficient at complex recognition tasks. In this work, we venture into the relatively unexplored area of utilizing the inherent device stochasticity of such neuromimetic devices to model complex neural functionalities in a probabilistic framework in the time domain. We consider the implementation of a Deep Spiking Neural Network capable of performing high accuracy and low latency classification tasks where the neural computing unit is enabled by the stochastic switching behavior of a Magnetic Tunnel Junction. Simulation studies indicate an energy improvement of $20\times$ over a baseline CMOS design in $45nm$ technology.

cs.ET↗
arXiv2016

Significance Driven Hybrid 8T-6T SRAM for Energy-Efficient Synaptic Storage in Artificial Neural Networks

Multilayered artificial neural networks (ANN) have found widespread utility in classification and recognition applications. The scale and complexity of such networks together with the inadequacies of general purpose computing platforms have led to a significant interest in the development of efficient hardware implementations. In this work, we focus on designing energy efficient on-chip storage for the synaptic weights. In order to minimize the power consumption of typical digital CMOS implementations of such large-scale networks, the digital neurons could be operated reliably at scaled voltages by reducing the clock frequency. On the contrary, the on-chip synaptic storage designed using a conventional 6T SRAM is susceptible to bitcell failures at reduced voltages. However, the intrinsic error resiliency of NNs to small synaptic weight perturbations enables us to scale the operating voltage of the 6TSRAM. Our analysis on a widely used digit recognition dataset indicates that the voltage can be scaled by 200mV from the nominal operating voltage (950mV) for practically no loss (less than 0.5%) in accuracy (22nm predictive technology). Scaling beyond that causes substantial performance degradation owing to increased probability of failures in the MSBs of the synaptic weights. We, therefore propose a significance driven hybrid 8T-6T SRAM, wherein the sensitive MSBs are stored in 8T bitcells that are robust at scaled voltages due to decoupled read and write paths. In an effort to further minimize the area penalty, we present a synaptic-sensitivity driven hybrid memory architecture consisting of multiple 8T-6T SRAM banks. Our circuit to system-level simulation framework shows that the proposed synaptic-sensitivity driven architecture provides a 30.91% reduction in the memory access power with a 10.41% area overhead, for less than 1% loss in the classification accuracy.

cs.NE↗
arXiv2016

Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing

Large-scale artificial neural networks have shown significant promise in addressing a wide range of classification and recognition applications. However, their large computational requirements stretch the capabilities of computing platforms. The fundamental components of these neural networks are the neurons and its synapses. The core of a digital hardware neuron consists of multiplier, accumulator and activation function. Multipliers consume most of the processing energy in the digital neurons, and thereby in the hardware implementations of artificial neural networks. We propose an approximate multiplier that utilizes the notion of computation sharing and exploits error resilience of neural network applications to achieve improved energy consumption. We also propose Multiplier-less Artificial Neuron (MAN) for even larger improvement in energy consumption and adapt the training process to ensure minimal degradation in accuracy. We evaluated the proposed design on 5 recognition applications. The results show, 35% and 60% reduction in energy consumption, for neuron sizes of 8 bits and 12 bits, respectively, with a maximum of ~2.83% loss in network accuracy, compared to a conventional neuron implementation. We also achieve 37% and 62% reduction in area for a neuron size of 8 bits and 12 bits, respectively, under iso-speed conditions.

cs.NE↗
arXiv2016

Unsupervised Regenerative Learning of Hierarchical Features in Spiking Deep Networks for Object Recognition

We present a spike-based unsupervised regenerative learning scheme to train Spiking Deep Networks (SpikeCNN) for object recognition problems using biologically realistic leaky integrate-and-fire neurons. The training methodology is based on the Auto-Encoder learning model wherein the hierarchical network is trained layer wise using the encoder-decoder principle. Regenerative learning uses spike-timing information and inherent latencies to update the weights and learn representative levels for each convolutional layer in an unsupervised manner. The features learnt from the final layer in the hierarchy are then fed to an output layer. The output layer is trained with supervision by showing a fraction of the labeled training dataset and performs the overall classification of the input. Our proposed methodology yields 0.92%/29.84% classification error on MNIST/CIFAR10 datasets which is comparable with state-of-the-art results. The proposed methodology also introduces sparsity in the hierarchical feature representations on account of event-based coding resulting in computationally efficient learning.

cs.NE↗
arXiv2016

Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets

Non-Boolean computing based on emerging post-CMOS technologies can potentially pave the way for low-power neural computing platforms. However, existing work on such emerging neuromorphic architectures have either focused on solely mimicking the neuron, or the synapse functionality. While memristive devices have been proposed to emulate biological synapses, spintronic devices have proved to be efficient at performing the thresholding operation of the neuron at ultra-low currents. In this work, we propose an All-Spin Artificial Neural Network where a single spintronic device acts as the basic building block of the system. The device offers a direct mapping to synapse and neuron functionalities in the brain while inter-layer network communication is accomplished via CMOS transistors. To the best of our knowledge, this is the first demonstration of a neural architecture where a single nanoelectronic device is able to mimic both neurons and synapses. The ultra-low voltage operation of low resistance magneto-metallic neurons enables the low-voltage operation of the array of spintronic synapses, thereby leading to ultra-low power neural architectures. Device-level simulations, calibrated to experimental results, was used to drive the circuit and system level simulations of the neural network for a standard pattern recognition problem. Simulation studies indicate energy savings by ~ 100x in comparison to a corresponding digital/ analog CMOS neuron implementation.

cs.ET↗
arXiv2016

Conditional Deep Learning for Energy-Efficient and Enhanced Pattern Recognition

Deep learning neural networks have emerged as one of the most powerful classification tools for vision related applications. However, the computational and energy requirements associated with such deep nets can be quite high, and hence their energy-efficient implementation is of great interest. Although traditionally the entire network is utilized for the recognition of all inputs, we observe that the classification difficulty varies widely across inputs in real-world datasets; only a small fraction of inputs require the full computational effort of a network, while a large majority can be classified correctly with very low effort. In this paper, we propose Conditional Deep Learning (CDL) where the convolutional layer features are used to identify the variability in the difficulty of input instances and conditionally activate the deeper layers of the network. We achieve this by cascading a linear network of output neurons for each convolutional layer and monitoring the output of the linear network to decide whether classification can be terminated at the current stage or not. The proposed methodology thus enables the network to dynamically adjust the computational effort depending upon the difficulty of the input data while maintaining competitive classification accuracy. We evaluate our approach on the MNIST dataset. Our experiments demonstrate that our proposed CDL yields 1.91x reduction in average number of operations per input, which translates to 1.84x improvement in energy. In addition, our results show an improvement in classification accuracy from 97.5% to 98.9% as compared to the original network.

cs.CV↗
arXiv2015

Spin-Torque Sensors for Energy Efficient High Speed Long Interconnects

In this paper, we propose a Spin-Torque (ST) based sensing scheme that can enable energy efficient multi-bit long distance interconnect architectures. Current-mode interconnects have recently been proposed to overcome the performance degradations associated with conventional voltage mode Copper (Cu) interconnects. However, the performance of current mode interconnects are limited by analog current sensing transceivers and equalization circuits. As a solution, we propose the use of ST based receivers that use Magnetic Tunnel Junctions (MTJ) and simple digital components for current-to-voltage conversion and do not require analog transceivers. We incorporate Spin-Hall Metal (SHM) in our design to achieve high speed sensing. We show both single and multi-bit operations that reveal major benefits at higher speeds. Our simulation results show that the proposed technique consumes only 3.93-4.72 fJ/bit/mm energy while operating at 1-2 Gbits/sec; which is considerably better than existing charge based interconnects. In addition, Voltage Controlled Magnetic Anisotropy (VCMA) can reduce the required current at the sensor. With the inclusion of VCMA, the energy consumption can be further reduced to 2.02-4.02 fJ/bit/mm

cs.ET↗
arXiv2015

Energy Efficient and High Performance Current-Mode Neural Network Circuit using Memristors and Digitally Assisted Analog CMOS Neurons

Emerging nano-scale programmable Resistive-RAM (RRAM) has been identified as a promising technology for implementing brain-inspired computing hardware. Several neural network architectures, that essentially involve computation of scalar products between input data vectors and stored network weights can be efficiently implemented using high density cross-bar arrays of RRAM integrated with CMOS. In such a design, the CMOS interface may be responsible for providing input excitations and for processing the RRAM output. In order to achieve high energy efficiency along with high integration density in RRAM based neuromorphic hardware, the design of RRAM-CMOS interface can therefore play a major role. In this work we propose design of high performance, current mode CMOS interface for RRAM based neural network design. The use of current mode excitation for input interface and design of digitally assisted current-mode CMOS neuron circuit for the output interface is presented. The proposed technique achieve 10x energy as well as performance improvement over conventional approaches employed in literature. Network level simulations show that the proposed scheme can achieve 2 orders of magnitude lower energy dissipation as compared to a digital ASIC implementation of a feed-forward neural network.

cs.ET↗
arXiv2015

High Sensitivity Biosensor using Injection Locked Spin Torque Nano-Oscillators

With ever increasing research on magnetic nano systems it is shown to have great potential in the areas of magnetic storage, biosensing, magnetoresistive insulation etc. In the field of biosensing specifically Spin Valve sensors coupled with Magnetic Nanolabels is showing great promise due to noise immunity and energy efficiency [1]. In this paper we present the application of injection locked based Spin Torque Nano Oscillator (STNO) suitable for high resolution energy efficient labeled DNA Detection. The proposed STNO microarray consists of 20 such devices oscillating at different frequencies making it possible to multiplex all the signals using capacitive coupling. Frequency Division Multiplexing can be aided with Time division multiplexing to increase the device integration and decrease the readout time while maintaining the same efficiency in presence of constant input referred noise.

cs.ET↗
arXiv2015

Modeling and Simulation of Spin Transfer Torque Generated at Topological Insulator/Ferromagnetic Heterostructure

Topological Insulator (TI) has recently emerged as an attractive candidate for possible application to spintronic circuits because of its strong spin orbit coupling. TIs are unique materials that have an insulating bulk but conducting surface states due to band inversion and these surface states are protected by time reversal symmetry. In this paper, we propose a physics-based spin dynamics simulation framework for TI/Ferromagnet (TI/FM) bilayer heterostructures that is able to capture the electronic band structure of a TI while calculating the electron and spin transport properties. Our model differs from TI/FM models proposed in the literature in that it is able to account for the 3D band structure of TIs and the effect of exchange coupling and external magnetic field on the band structure. Our proposed approach uses 2D surface Hamiltonian for TIs that includes all necessary features for spin transport calculations so as to properly model the characteristics of a TI/FM heterostructure. Using this Hamiltonian and appropriate parameters, we show that the effect of quantum confinement and exchange coupling are successfully captured in the calculated surface band structure compared with the quantum well band diagram of a 3D TI, and matches well with experimental data reported in the literature. We then show how this calibrated Hamiltonian is used with the self-consistent non equilibrium Green's functions (NEGF) formalism to determine the charge and spin transport in TI/FM bilayer heterostructures. Our calculations agree well with experimental data and capture the unique features of a TI/FM heterostructure such as high spin Hall angle, high spin conductivity etc. Finally, we show how the results obtained from NEGF calculations may be incorporated into the Landau-Lifshitz-Gilbert-Slonczewski (LLGS) formulation to simulate the magnetization dynamics of an FM layer sitting on top of a TI.

cond-mat.mtrl-sci↗
arXiv2015

Exploring Spin-Transfer-Torque Devices for Logic Applications

As CMOS nears the end of the projected scaling roadmap, significant effort has been devoted to the search for new materials and devices that can realize memory and logic. Spintronics, is one of the promising directions for the Post-CMOS era. While the potential of spintronic memories is relatively well known, realizing logic remains an open and critical challenge. All Spin Logic (ASL) is a recently proposed logic style that realizes Boolean logic using spin-transfer-torque (STT) devices based on the principle of non-local spin torque. ASL has advantages such as density, non-volatility, and low operating voltage. However, it also suffers from drawbacks such as low speed and static power dissipation. Recent work has shown that, in the context of simple arithmetic circuits (adders, multipliers), the efficiency of ASL can be greatly improved using techniques that utilize its unique characteristics. An evaluation of ASL across a broad range of circuits, considering the known optimization techniques, is an important next step in determining its viability. In this work, we propose a systematic methodology for the synthesis of ASL circuits. Our methodology performs various optimizations that benefit ASL, such as intra-cycle power gating, stacking of ASL nanomagnets, and fine-grained logic pipelining. We utilize the proposed methodology to evaluate the suitability of ASL implementations for a wide range of benchmarks viz. random combinational and sequential logic, digital signal processing circuits, and the Leon SPARC3 general-purpose processor. Based on our evaluation, we identify (i) the large current requirement of nanomagnets at fast switching speeds, (ii) the static power dissipation in the all-metallic devices, and (iii) the short spin flip length in interconnects as key bottlenecks that limit the competitiveness of ASL.

cond-mat.mes-hall↗
arXiv2014

STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks

Recent years have witnessed growing interest in the use of Artificial Neural Networks (ANNs) for vision, classification, and inference problems. An artificial neuron sums N weighted inputs and passes the result through a non-linear transfer function. Large-scale ANNs impose very high computing requirements for training and classification, leading to great interest in the use of post-CMOS devices to realize them in an energy efficient manner. In this paper, we propose a spin-transfer-torque (STT) device based on Domain Wall Motion (DWM) magnetic strip that can efficiently implement a Soft-limiting Non-linear Neuron (SNN) operating at ultra-low supply voltage and current. In contrast to previous spin-based neurons that can only realize hard-limiting transfer functions, the proposed STT-SNN displays a continuous resistance change with varying input current, and can therefore be employed to implement a soft-limiting neuron transfer function. Soft-limiting neurons are greatly preferred to hard-limiting ones due to their much improved modeling capacity, which leads to higher network accuracy and lower network complexity. We also present an ANN hardware design employing the proposed STT-SNNs and Memristor Crossbar Arrays (MCA) as synapses. The ultra-low voltage operation of the magneto metallic STT-SNN enables the programmable MCA-synapses, computing analog-domain weighted summation of input voltages, to also operate at ultra-low voltage. We modeled the STT-SNN using micro-magnetic simulation and evaluated them using an ANN for character recognition. Comparisons with analog and digital CMOS neurons show that STT-SNNs can achieve more than two orders of magnitude lower energy consumption.

cs.ET↗