Kemi Xu | Searcharxiv

arXiv2026

Orientation-tunable correlated Chern insulating states in chiral twisted double bilayer graphene proximitized by WSe2

Moire flat bands in graphene systems proximitized by transition-metal dichalcogenides (TMDCs) provide a setting where spin-orbit coupling (SOC) can reshape band topology. The crystallographic alignment angle twist angle between TMDC and graphene layers is predicted to tune the balance of Ising and Rashba SOC, but a combined theoretical and experimental understanding of how twist angle governs the topological character of correlated states has not been systematically established. Here we show that in chiral-stacked twisted double bilayer graphene in proximity to WSe2, twist angle between graphene and WSe2 determines the topological character of correlated Chern insulators. Continuum model calculations reveal that Ising spin-orbit coupling dominates at zero twist angle, giving rise to flat bands with finite valley Chern numbers, whereas Rashba coupling dominates at larger twist angle, resulting in topologically trivial bands. Transport measurements at quarter filling confirm this picture: twist angle = 0 deg devices exhibit C = +1 Chern insulators, consistent with spontaneous isospin polarization, whereas twist angle = 15 degree devices show C = 0 despite exhibiting similar correlated insulating behavior. The sharp contrast establishes crystallographic alignment as a new tuning knob, complementary to twist angle, displacement field, and carrier density, for engineering correlated topological states in van der Waals heterostructures.

cond-mat.mes-hall↗

arXiv2026

Parameter Efficient Machine Unlearning on Hybrid Resistive Memory based Compute-in-Memory Accelerators

Resistive memory compute-in-memory accelerators provide energy efficient analogue matrix vector multiplication for neural network inference, but frequent reprogramming of analogue weights remains costly because of device variability and iterative write and verify operations. This limitation hinders their use in edge model adaptation, including approximate machine unlearning and continual learning, where model parameters may need to be updated repeatedly in response to data deletion requests or newly arriving tasks. Here we present a co-design approach across hardware and software that maps frozen pretrained weights to analogue resistive memory arrays while placing trainable low rank adaptation branches in SRAM connected digital compute. By using LoRA style parameter efficient updates, the proposed scheme confines adaptation to a small set of digital parameters and avoids repeated reprogramming of the analogue backbone. To our knowledge, this work provides the first experimental demonstration of approximate machine unlearning on a fabricated resistive memory CIM accelerator. We validate the framework on a 180 nm 128x128 1T1R resistive-memory macro for face recognition, and through circuit-accurate simulations for speaker authentication and stylized image generation tasks, owing to the substantial model sizes involved. Compared with a baseline that directly updates analog weights, our hybrid mapping reduces analog training/update cost by up to 148x, on-chip deployment overhead by up to 388x, and inference energy by up to 59x, while preserving competitive task performance. These results show that hybrid analogue-digital LoRA mapping can enable efficient post-deployment adaptation on RM-CIM hardware, although formal machine-unlearning guarantees and large-scale system integration remain open challenges.

cs.ET↗