arXiv subjects

Kieran Dalton

Publications and source records attributed to Kieran Dalton.

6 recordsLinked to original sources

arXiv2026

Microwave Crosstalk in Planar Superconducting Quantum Devices

Microwave crosstalk poses a major challenge to scaling superconducting quantum devices as it introduces excess control errors. Although its magnitude and impact have been explored in various experimental settings, quantitative physical models capable of explaining measured crosstalk for a given device geometry remain scarce. Here, we address this gap by investigating microwave crosstalk in planar superconducting devices with crossovers. We identify two structures that can lead to strong crosstalk: a drive line routed in close proximity to another qubit, and a drive line crossing a qubit-qubit coupler using an air bridge. We design and characterize devices involving these structures and develop physical models that quantitatively explain the experimentally observed crosstalk. Based on these models, we discuss the design considerations for reducing microwave crosstalk. Our results provide practical guidance for low-crosstalk device layouts and establish a basis for the systematic investigation of weaker crosstalk mechanisms.

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arXiv2026

Blind Quantum Computation on a Modular Superconducting Processor

Current cloud-based quantum processors offer access to advanced hardware hosted on a remote server, but do not guarantee data or algorithm privacy. Blind quantum computation provides information-theoretic privacy by enabling a client to execute an algorithm without disclosing information about either the task or the final result. Here, we execute a measurement-based blind quantum computation protocol on a superconducting processor comprising two flip-chip-bonded modules, one acting as a server and the other as a client. The server generates a two-dimensional cluster state and forwards it to the client. Using this resource, the client implements a universal gate set with only adaptive single-qubit rotations and measurements. To illustrate this approach, we execute a three-qubit instance of the Deutsch-Jozsa algorithm. We analyze the server's quantum state after each rotation of a measurement-based single-qubit gate to verify that negligible information about the computation is revealed to the server, consistent with the one-way flow of information that guarantees blindness. This proof-of-principle demonstration establishes key elements of blind quantum computation in superconducting-circuit architectures, indicating that intermediate-scale implementations of blind protocols may become feasible with realistic near-term improvements in gate fidelities.

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arXiv2025

Resource-Efficient Cross-Platform Verification with Modular Superconducting Devices

Large-scale quantum computers are expected to benefit from modular architectures. Validating the capabilities of modular devices requires benchmarking strategies that assess performance within and between modules. In this work, we evaluate cross-platform verification protocols, which are critical for quantifying how accurately different modules prepare the same quantum state -- a key requirement for modular scalability and system-wide consistency. We demonstrate these algorithms using a six-qubit flip-chip superconducting quantum device consisting of two three-qubit modules on a single carrier chip, with connectivity for intra- and inter-module entanglement. We examine how the resource requirements of protocols relying solely on classical communication between modules scale exponentially with qubit number, and demonstrate that introducing an inter-module two-qubit gate enables sub-exponential scaling in cross-platform verification. This approach reduces the number of repetitions required by a factor of four for three-qubit states, with greater reductions projected for larger and higher-fidelity devices.

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arXiv2025

Performance Characterization of a Multi-Module Quantum Processor with Static Inter-Chip Couplers

Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. Modular architectures, in which circuit elements are spread over multiple chips, can further improve scalability and performance by enabling the integration of elements with different substrates or fabrication processes, by increasing the fabrication yield of completed devices, and by physically separating the qubits onto distinct modules to avoid correlated errors mediated by a common substrate. We present a design for a multi-chip module comprising one carrier chip and four qubit modules. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of $9 \times 10^{-3}$ in 200 ns. We calibrate single-qubit gates and measure a mean simultaneous randomized benchmarking error of $6 \times 10^{-4}$, consistent with the coherence times of the qubits. Using a wiring-efficient static inter-module coupler featuring galvanic inter-chip transitions, we demonstrate a controlled-Z two-qubit gate in 100 ns with an error of $7 \times 10^{-3}$ extracted from interleaved randomized benchmarking. Three-dimensional integration, as presented here, will continue to contribute to improving the performance of gates and readout as well as increasing the qubit count in future superconducting quantum processors.

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arXiv2024

Quantifying the effect of gate errors on variational quantum eigensolvers for quantum chemistry

Variational quantum eigensolvers (VQEs) are leading candidates to demonstrate near-term quantum advantage. Here, we conduct density-matrix simulations of leading gate-based VQEs for a range of molecules. We numerically quantify their level of tolerable depolarizing gate-errors. We find that: (i) The best-performing VQEs require gate-error probabilities between $10^{-6}$ and $10^{-4}$ ( $10^{-4}$ and $10^{-2}$ with error mitigation) to predict, within chemical accuracy, ground-state energies of small molecules with $4-14$ orbitals. (ii) ADAPT-VQEs that construct ansatz circuits iteratively outperform fixed-circuit VQEs. (iii) ADAPT-VQEs perform better with circuits constructed from gate-efficient rather than physically-motivated elements. (iv) The maximally-allowed gate-error probability, $p_c$, for any VQE to achieve chemical accuracy decreases with the number $\ncx$ of noisy two-qubit gates as $p_c\approxprop\ncx^{-1}$. Additionally, $p_c$ decreases with system size, even with error mitigation, implying that larger molecules require even lower gate-errors. Thus, quantum advantage via gate-based VQEs is unlikely unless gate-error probabilities are decreased by orders of magnitude.

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arXiv2023

Layering and subpool exploration for adaptive Variational Quantum Eigensolvers: Reducing circuit depth, runtime, and susceptibility to noise

Adaptive variational quantum eigensolvers (ADAPT-VQEs) are promising candidates for simulations of strongly correlated systems on near-term quantum hardware. To further improve the noise resilience of these algorithms, recent efforts have been directed towards compactifying, or layering, their ansatz circuits. Here, we broaden the understanding of the algorithmic layering process in three ways. First, we investigate the non-commutation relations between the different elements that are used to build ADAPT-VQE ansätze. Doing so, we develop a framework for studying and developing layering algorithms, which produce shallower circuits. Second, based on this framework, we develop a new subroutine that can reduce the number of quantum-processor calls by optimizing the selection procedure with which a variational quantum algorithm appends ansatz elements. Third, we provide a thorough numerical investigation of the noise-resilience improvement available via layering the circuits of ADAPT-VQE algorithms. We find that layering leads to an improved noise resilience with respect to amplitude-damping and dephasing noise, which, in general, affect idling and non-idling qubits alike. With respect to depolarizing noise, which tends to affect only actively manipulated qubits, we observe no advantage of layering.

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