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Kisoo Nam

Publications and source records attributed to Kisoo Nam.

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Size-Dependent Band-Tail Localization in Oxide Semiconductors Revealed by Direct Density-of-States Mapping

Disorder-induced localization is expected to become increasingly important as amorphous oxide semiconductor transistors are scaled toward low-dimensional channels, yet the electronic states responsible for this transport regime remain difficult to resolve experimentally. Here, we use a lock-in-based electric-field penetration technique to directly map the effective density of states (DOS) in In-based oxide semiconductor thin-film transistors (TFTs). The extracted quantum capacitance, carrier density, and chemical potential reveal a disorder-dominated transport regime in which band-tail states are not merely passive traps, but become screening-active and partially transport-active. Geometry-dependent DOS mapping shows an exponential suppression of the effective DOS with channel length, demonstrating size-dependent band-tail localization and providing a microscopic origin for a distinct localization-induced threshold-voltage roll-off mechanism. Temperature-dependent measurements show that the disorder-dominated DOS is strongly suppressed at low temperatures, while extended diffusive states remain nearly unchanged, confirming the localization origin. By tuning film thickness, O2 annealing, and In/Ga/Zn composition, we further demonstrate systematic suppression of disorder and effective-DOS localization. This work establishes direct DOS mapping as a device-level probe of localization physics and provides a pathway for engineering disorder in low-dimensional oxide semiconductor electronics.

cond-mat.mes-hall

200 mm Wafer-Scale Monolithic 3D Integration of Atomic Layer-Deposited Oxide Semiconductors

Monolithic 3D (M3D) integration offers a pathway to overcome the scaling limits of conventional silicon complementary metal-oxide-semiconductor (CMOS) technology by extending dense vertical stacking of multifunctional logic and memory devices. Here, we demonstrate wafer-scale M3D integration of three tiers of atomic-layer-deposited (ALD) indium oxide (InOx)-based devices (>100,000 fabricated), including ferroelectric, enhancement-mode, and depletion-mode field-effect transistors, on 200 mm silicon wafers. We achieve threshold voltage standard deviation as low as 0.04 V, average electron mobility up to 91.6 cm2V-1s-1, and fully functional cross-tier circuits. A four-tier 3D computing-in-memory (CIM) accelerator targeting large language model workloads is developed using a custom InOx process design kit, delivering 1.4x to 2.9x speedup and comparable energy-delay product improvements over 2D baselines. These results establish ALD InOx M3D integration as a scalable and CMOS-compatible platform for next-generation artificial intelligence hardware and advanced electronics.

physics.app-ph