arXiv subjects

Kosuke Nagashio

Publications and source records attributed to Kosuke Nagashio.

At least 19 recordsLinked to original sources

arXiv2020

Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage

The memory window of floating gate (FG) type non-volatile memory (NVM) devices is a fundamental figure of merit used not only to evaluate the performance, such as retention and endurance, but also to discuss the feasibility of advanced functional memory devices. However, the memory window of two dimensional (2D) materials based NVM devices is historically determined from round sweep transfer curves, while that of conventional Si NVM devices is determined from high and low threshold voltages (Vths), which are measured by single sweep transfer curves. Here, it is elucidated that the memory window of 2D NVM devices determined from round sweep transfer curves is overestimated compared with that determined from single sweep transfer curves. The floating gate voltage measurement proposed in this study clarifies that the Vths in round sweep are controlled not only by the number of charges stored in floating gate but also by capacitive coupling between floating gate and back gate. The present finding on the overestimation of memory window enables to appropriately evaluate the potential of 2D NVM devices.

cond-mat.mtrl-sci↗

arXiv2020

All 2D Heterostructure Tunnel Field Effect Transistors: Impact of Band Alignment and Heterointerface Quality

Van der Waals heterostructures are the ideal material platform for tunnel field effect transistors (TFETs) because a band-to-band tunneling (BTBT) dominant current is feasible at room temperature (RT) due to ideal, dangling bond free heterointerfaces. However, achieving subthreshold swing (SS) values lower than 60 mVdec-1 of the Boltzmann limit is still challenging. In this work, we systematically studied the band alignment and heterointerface quality in n-MoS2 channel heterostructure TFETs. By selecting a p+-MoS2 source with a sufficiently high doping level, stable gate modulation to a type III band alignment was achieved regardless of the number of MoS2 channel layers. For the gate stack formation, it was found that the deposition of Al2O3 as the top gate introduces defect states for the generation current under reverse bias, while the integration of an h-BN top gate provides a defect-free, clean interface, resulting in the BTBT dominant current even at RT. All 2D heterostructure TFETs produced by combining the type III n-MoS2/p+-MoS2 heterostructure with the h-BN top gate insulator resulted in low SS values at RT.

cond-mat.mtrl-sci↗

arXiv2020

Understanding interface properties in 2D heterostructure FETs

Fifteen years have passed since graphene was first isolated on the substrate from bulk graphite. During that period, 2D layered materials with intrinsic band gaps have been realized. Although many exciting results have been reported for both their fundamental physics and applications, the discussion of 2D electron device application to the future integrated circuit is still based on the expectation of the inherently high properties that 2D materials ideally possess. This review article focuses on the gate stack property, which is one of most important building blocks in the field effect transistor. Starting from the comparison of the 2D/SiO2 interface properties with the conventional SiO2/Si interface properties, recent advances in the studies of gate stack properties for bilayer graphene and MoS2 FETs are discussed. In particular, the advantages and disadvantages of the 2D heterostructures with 2D insulator of h-BN are emphasized. This review may provide conceptual and experimental approaches for controlling the 2D heterointerface properties.

cond-mat.mtrl-sci↗

arXiv2019

Quantum-mechanical effect in atomically thin MoS2 FET

Two-dimensional (2D) layered materials-based field-effect transistors (FETs) are promising for ultimate scaled electron device applications because of the improved electrostatics to atomically thin body thickness. However, compared with the typical thickness of ~5-nm for Si-on-insulator (SOI), the advantage of the ultimate thickness limit of monolayer for the device performance has not been fully proved yet, especially for the on-state at the accumulation region. Here, we present much stronger quantum-mechanical effect at the accumulation region based on the C-V analysis for top-gate MoS2 FETs. The self-consistent calculation elucidated that the electrons are confined in the monolayer thickness, unlike in the triangle potential formed by the electric field for SOI, the gate-channel capacitance is ideally maximized to the gate insulator capacitance since the capacitive contribution of the channel can be neglected due to the negligible channel thickness. This quantum-mechanical effect agreed well with the experimental results. Therefore, monolayer 2D channels are suggested to be used to enhance the on-current as well as the gate modulation ability.

physics.app-ph↗

arXiv2019

Integrating high-quality dielectrics with one-nanometer equivalent oxide thickness on two-dimensional electronic devices

Two-dimensional (2D) semiconductors are widely recognized as attractive channel materials for low-power electronics. However, an unresolved challenge is the integration of high-quality, ultrathin high-\k{appa} dielectrics that fully meet the roadmap requirements for low-power applications. With a dangling-bond free surface, the deposition of dielectrics by atomic layer deposition (ALD) on 2D materials is usually characterized with non-uniform nucleation and island formation, producing a highly porous dielectric layer with serious leakage particularly at the small equivalent oxide thickness (EOT) limit. Here, we report the robust ALD of highly uniform high-\k{appa} dielectric on 2D semiconductors by using ~0.3 nm-thick exclusively monolayer molecular crystal as seeding layer. Ultrathin dielectrics down to 1 nm EOT is realized on graphene, MoS2 and WSe2, with considerably reduced roughness, density of interface states, leakage current and improved breakdown field compared to prior methods. Taking advantage of the reduced EOT, we demonstrate graphene RF transistors operating at 60 GHz, as well as MoS2 and WSe2 complementary metal-oxide-semiconductor (CMOS) transistors with Vdd =0.8 V and ideal subthreshold swing (SS) of 60 mV/dec, 20 nm-channel-length MoS2 transistors with on/off ratio over 10^7. These studies highlight that our dielectric integration method is generally applicable for different 2D materials, and compatible with top-down fabrication process on large-area chemical vapor deposited films.

physics.app-ph↗

arXiv2019

Influence of interface dipole layers on the performance of graphene field effect transistors

The linear band dispersion of graphene's bands near the Fermi level gives rise to its unique electronic properties, such as a giant carrier mobility, and this has triggered extensive research in applications, such as graphene field-effect transistors (GFETs). However, GFETs generally exhibit a device performance much inferior compared to the expected one. This has been attributed to a strong dependence of the electronic properties of graphene on the surrounding interfaces. Here we study the interface between a graphene channel and SiO$_{2}$, and by means of photoelectron spectromicroscopy achieve a detailed determination of the course of band alignment at the interface. Our results show that the electronic properties of graphene are modulated by a hydrophilic SiO$_{2}$ surface, but not by a hydrophobic one. By combining photoelectron spectromicroscopy with GFET transport property characterization, we demonstrate that the presence of electrical dipoles in the interface, which reflects the SiO$_{2}$ surface electrochemistry, determines the GFET device performance. A hysteresis in the resistance vs. gate voltage as a function of polarity is ascribed to a reversal of the dipole layer by the gate voltage. These data pave the way for GFET device optimization.

cond-mat.mtrl-sci↗

arXiv2019

Pinpoint pick-up and bubble-free assembly of 2D materials using PDMS/PMMA polymers with lens shapes

The key to achieving high-quality van der Waals heterostructure devices made by stacking two-dimensional (2D) layered materials lies in having a clean interface without interfacial bubbles and wrinkles. In this study, the pinpoint pick-up and transfer system of 2D crystals is constructed using polymers with lens shapes. We report the bubble-free and clean-interface assembly of 2D crystals in which unidirectional sweep of the transfer interface precisely controlled with the help of the inclined substrate pushes the bubbles away from the interface.

physics.app-ph↗

arXiv2018

Accumulation-mode two-dimensional field-effect transistor: Operation mechanism and thickness scaling rule

Understanding the operation mode of a two-dimensional (2D) material-based field-effect transistor (FET) is one of the most essential issues in the study of electronics and physics. The existing Schottky barrier-FET model for devices with global back gate and metallic contacts overemphasizes the metal-2D contact effect, and the widely observed residual conductance cannot be explained by this model. Here, an accumulation-mode FET model, which directly reveals 2D channel transport properties, is developed based on a partial top-gate MoS2 FET with metallic contacts and a channel thickness of 0.65~118 nm. The operation mechanism of an accumulation-mode FET is validated and clarified by carefully performed capacitance measurements. A depletion capacitance-quantum capacitance transition is observed. After the analysis of the MoS2 accumulation-mode FET, we have confirmed that most 2D-FETs show accumulation-mode behavior. The universal thickness scaling rule of 2D-FETs is then proposed, which provides guidance for future research on 2D materials.

cond-mat.mtrl-sci↗

arXiv2018

Direct observation of electron capture & emission processes by the time domain charge pumping measurement of MoS2 FET

Understanding interface properties in MoS2 field effect transistors with a high-k gate insulator is critical for improving the performance of the device. Here, by applying the time domain charge pumping method, the elementary process for capture and emission of electrons to the interface states is monitored directly using a fast acquisition system. The main outcome is the detection of the clear difference in the capture and emission process of electrons to the interface states. In addition to the transient current response for gate capacitance, the current peak is observed during electron capture, while the broad tail is detected during electron emission. This different behavior is associated with the fact that the time constant for electron capture is much shorter than that for electron emission. Moreover, Dit is evaluated to be in the range of 1012 - 1013 cm-2 eV-1, which is comparable with that estimated from subthreshold swing.

physics.app-ph↗

arXiv2018

Electrically inert h-BN/bilayer graphene interface in all-2D-heterostructure FETs

Bilayer graphene field-effect transistors (BLG-FETs), unlike conventional semiconductors, are greatly sensitive to potential fluctuations due to the charged impurities in high-k gate stacks since the potential difference between two layers induced by the external perpendicular electrical filed is the physical origin behind the band gap opening. The assembly of BLG with layered h-BN insulators into van der Waals heterostructure has been widely recognized to achieve the superior electrical transport properties. However, the carrier response properties at the h-BN/BLG heterointerface, which control the device performance, have not yet been revealed due to the inevitably large parasitic capacitance. In this study, the significant reduction of potential fluctuations to ~1 meV is achieved in all-2-dimensional heterostructure BLG-FET on a quartz substrate, which results in the suppression of the off-current to the measurement limit at a small band gap of ~90 meV at 20 K. By capacitance measurement, we demonstrate that the electron trap/detrap response at such heterointerface is suppressed to undetectable level in the measurement frequency range. The electrically inert van der Waals heterointerface paves the way for the realization of future BLG electronics applications.

physics.app-ph↗

arXiv2018

2D Tunnel Field Effect Transistors (FETs) with a Stable Charge-Transfer-Type p$^+$-WSe$_2$ Source

Two-dimensional (2D) materials are highly promising for tunnel field effect transistors (TFETs) with low subthreshold swing and high drive current because the shorter tunnel distance and strong gate controllability can be expected from the van der Waals gap distance and the atomically sharp heterointerface formed independently of lattice matching. However, the common problem for 2D-2D TFETs is the lack of highly doped 2D materials with the high process stability as the sources. In this study, we have found that p+-WSe2 doped by charge transfer from a WOx surface oxide layer can be stabilized by transferring it onto a h-BN substrate. Using this p$^+$-WSe$_2$ as a source, we fabricate all-solid-state 2D-2D heterostructure TFETs with an Al2O3 top gate insulator, i.e., type-II p$^+$-WSe$_2$ /MoS$_2$ and type-III p$^+$-WSe$_2$ /WSe$_2$. The band-to-band tunneling and negative differential resistance trends are clearly demonstrated at low temperatures. This work suggests that high doped 2D crystal of the charge transfer type is an excellent choice as sources for TFETs.

physics.app-ph↗

arXiv2018

Determination of Carrier Polarity in Fowler-Nordheim Tunneling and Evidence of Fermi Level Pinning at the Hexagonal Boron Nitride / Metal Interface

Hexagonal boron nitride (h-BN) is an important insulating substrate for two-dimensional (2D) heterostructure devices and possesses high dielectric strength comparable to SiO2. Here, we report two clear differences in their physical properties. The first one is the occurrence of Fermi level pinning at the metal/h-BN interface, unlike that at the metal/SiO2 interface. The second one is that the carrier of Fowler-Nordheim (F-N) tunneling through h-BN is a hole, which is opposite to an electron in the case of SiO2. These unique characteristics are verified by I-V measurements in the graphene/h-BN/metal heterostructure device with the aid of a numerical simulation, where the barrier height of graphene can be modulated by a back gate voltage owing to its low density of states. Furthermore, from a systematic investigation using a variety of metals, it is confirmed that the hole F-N tunneling current is a general characteristic because the Fermi levels of metals are pinned in the small energy range around ~3.5 eV from the top of the conduction band of h-BN, with a pinning factor of 0.30. The accurate energy band alignment at the h-BN/metal interface provides practical knowledge for 2D heterostructure devices.

cond-mat.mtrl-sci↗

arXiv2018

Band tail interface states and quantum capacitance in a monolayer molybdenum disulfide field-effect-transistor

Although MoS2 field-effect transistors (FETs) with high-k dielectrics are promising for electron device applications, the underlying physical origin of interface degradation remains largely unexplored. Here, we present a systematic analysis of the energy distribution of the interface state density (Dit) and the quantum capacitance (CQ) in a dual-gate monolayer exfoliated MoS2 FET. The CQ analysis enabled us to construct a Dit extraction method as a function of EF. A band tail distribution of Dit with the lowest value of 8*1011 cm-2eV-1 suggests that Dit is not directly related to the sharp peak energy distribution of the S vacancy. Therefore, the Mo-S bond bending related to the strain at the interface or the surface roughness of the SiO2/Si substrate might be the origin. It is also shown that ultra-thin 2D materials are more sensitive to interface disorder due to the reduced density of states. Since all the constituents for the measured capacitance are well understood, I-V characteristics can be reproduced by utilizing the drift current model. As a result, one of the physical origins of the metal/insulator transition is suggested to be the external outcome of interface traps and quantum capacitance.

cond-mat.mtrl-sci↗

arXiv2017

Transport properties of the top and bottom surfaces in monolayer MoS2 grown by chemical vapor deposition

The advantage of MoS2, compared with graphene, is the direct growth on various oxide substrates by chemical vapor deposition (CVD) without utilizing catalytic metal substrates, which facilitates practical applications for electronics. The carrier mobility is, however, degraded from the intrinsic limit mainly due to short-range scattering caused by S vacancies formed during CVD growth. If the upper limit for the crystallinity of CVD-MoS2 on oxide substrates is determined by the MoS2/substrate interaction during growth, it will hinder the advantage. In this study, we investigated the interaction between monolayer MoS2 and a SiO2/Si substrate and the difference in crystallinity between the top and bottom S surfaces due to the MoS2/substrate interaction. Raman and photoluminescence spectroscopy indicated that doping and strain were induced in MoS2 from the substrate, but they could be removed by transferring MoS2 to a new substrate using polymers. The newly developed polymer-transfer technique enabled selective transfer of the bottom or top surface of CVD-MoS2 onto a new SiO2/Si substrate. The metal-insulator transition was clearly observed for both the normal and inverse transfers, suggesting that the crystallinity of CVD-MoS2 is high and that the crystallinity of the bottom surface interacting with the substrate was similar to that of the top free surface. These results provide positive prospects for the further improvement of the crystallinity of MoS2 on oxide substrates by reconsidering the growth conditions.

cond-mat.mtrl-sci↗

arXiv2016

Comparison of device structures for the dielectric breakdown measurement of hexagonal boron nitride

Improving the film quality in the synthesis of large-area hexagonal boron nitride films (h-BN) for two-dimensional material devices remains a great challenge. The measurement of electrical breakdown dielectric strength (EBD) is one of the most important methods to elucidate the insulating quality of h-BN. In this work, the EBD of high quality exfoliated single-crystal h-BN was investigated using three different electrode structures under different environmental conditions to determine the ideal electrode structure and environment for EBD measurement. A systematic investigation revealed that EBD is not sensitive to contact force or electrode area but strongly depends on the relative humidity during measurement. Once the measurement environment is properly managed, it was found that the EBD values are consistent within experimental error regardless of the electrode structure, which enables the evaluation of the crystallinity of synthesized h-BN at the microscopic and macroscopic level by utilizing the three different electrode structures properly for different purposes.

cond-mat.mtrl-sci↗

arXiv2016

Experimental detection of active defects in few layers MoS2 through random telegraphic signals analysis observed in its FET characteristics

Transition-metal dichalcogenides (TMDs), such as molybdenum disulfide (MoS2), are expected to be promising for next generation device applications. The existence of sulfur vacancies formed in MoS2, however, will potentially make devices unstable and problematic. Random telegraphic signals (RTSs) have often been studied in small area Si metal-oxide-semiconductor field-effect transistors (MOSFETs) to identify the carrier capture and emission processes at defects. In this paper, we have systemically analyzed RTSs observed in atomically thin layer MoS2 FETs. Several types of RTSs have been analyzed. One is the simple on/off type of telegraphic signals, the second is multilevel telegraphic signals with a superposition of the simple signals, and the third is multilevel telegraphic signals that are correlated with each other. The last one is discussed from the viewpoint of the defect-defect interaction in MoS2 FETs with a weak screening in atomically confined two-dimensional electron-gas systems. Furthermore, the position of defects causing RTSs has also been investigated by preparing MoS2 FETs with multi-probes. The electron beam was locally irradiated to intentionally generate defects in the MoS2 channel. It is clearly demonstrated that the MoS2 channel is one of the RTS origins. RTS analysis enables us to analyze the defect dynamics of TMD devices.

cond-mat.mtrl-sci↗

arXiv2016

Anisotropic Dielectric Breakdown Strength of Single Crystal Hexagonal Boron Nitride

Dielectric breakdown has historically been of great interest from the perspectives of fundamental physics and electrical reliability. However, to date, the anisotropy in the dielectric breakdown has not been discussed. Here, we report an anisotropic dielectric breakdown strength (EBD) for h-BN, which is used as an ideal substrate for two-dimensional (2D) material devices. Under a well-controlled relative humidity, EBD values in the directions both normal and parallel to the c axis (EBD+c & EBD//c) were measured to be 3 and 12 MV/cm, respectively. When the crystal structure is changed from sp3 of cubic-BN (c-BN) to sp2 of h-BN, EBD+c for h-BN becomes smaller than that for c-BN, while EBD//c for h-BN drastically increases. Therefore, h-BN can possess a relatively high EBD concentrated only in the direction parallel to the c axis by conceding a weak bonding direction in the highly anisotropic crystal structure. This explains why the EBD//c for h-BN is higher than that for diamond. Moreover, the presented EBD value obtained from the high quality bulk h-BN crystal can be regarded as the standard for qualifying the crystallinity of h-BN layers grown via chemical vapor deposition for future electronic applications.

cond-mat.mtrl-sci↗

arXiv2016

Buffer Layer Engineering on Graphene via Various Oxidation Methods for Atomic Layer Deposition

The integration of high-k oxide on graphene using atomic layer deposition requires an electrically reliable buffer layer. In this study, Y was selected as the buffer layer due to the highest oxidation ability in rare earth elements and various oxidation methods (atmospheric, high-pressure O2 and ozone) were applied to the Y metal buffer layer. By optimizing oxidation conditions of the top gate insulator, we successfully improve the capacitance of top gate Y2O3 insulator and demonstrate a large Ion/Ioff ratio for bilayer graphene under an external electric field.

cond-mat.mtrl-sci↗