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L. Y. Meng

Publications and source records attributed to L. Y. Meng.

2 recordsLinked to original sources

Experimental scaling of the scrape-off layer particle flux width by outboard divertor Langmuir probes with favorable Bt configuration on EAST

The scrape-off layer (SOL) power width (λ_q) is important for predicting the heat load on divertor targets for future magnetically confined devices. Currently, the underlying physics for λ_q scaling is not fully understood. This paper extends the previous inboard SOL particle flux width (λ_{js}) scaling [Liu et al 2019 Plasma Phys. Control. Fusion 61 045001] to the outboard side in EAST, which can provide more experimental evidence for λ_q study. A systematic method has been developed to correct the less reliable upper outer (UO) divertor Langmuir probe (Div-LP) measurements with their more reliable neighboring measurements to reduce the measurement uncertainty of λ_js. For the discharges with the favorable Bt and upper single null configurations in the 2019 experiment campaign, about 260 discharges have been selected by certain criteria to ensure good λ_js measurements. Three H-mode, L-mode, and Ohmic databases have been constructed and are used for λ_js scalings. It is found that the outboard λ_js for the H-mode and L-mode plasmas scales as, λ_(js,UO)=1.52(W_{MHD}/n_e)^(-0.61) P_{tot}^0.19, where W_{MHD} is the stored energy, n_e is the line-averaged density, and P_{tot} is the total input power. This scaling is similar to the inboard λ_js scaling except for the scaling amplitude that is probably due the triangularity. The repeatable scaling dependence on W_{MHD}/n_e confirms the reliability of this dependence even though the regression quality is relatively poor. It is also discussed that the solely scaling of λ_q/λ_{js} on Bp is not enough to include all the physics of SOL heat transports.

physics.plasm-ph

New Multi-Scale Simulation Framework for Next-Generation Electronic Design Automation with Application to the Junctionless Transistor

In this paper we present a new multi-scale simulation scheme for next-generation electronic design automation for nano-electronics. The scheme features a combination of the first-principles quantum mechanical calculation, semi-classical semiconductor device simulation, compact model generation and circuit simulation. To demonstrate the feasibility of the proposed scheme, we apply our newly developed quantum mechanics/electromagnetics method to simulate the junctionless transistors. The simulation results are consistent with the experimental measurements and provide new insights on the depletion effect of the hetero-doped gate on the drain current. Based on the calculated I-V curves, a compact model is then constructed for the junctionless transistors. The validity of the compact model is further verified by the transient circuit simulation of an inverter.

cond-mat.mes-hall