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Lassi Lehtisyrjä

Publications and source records attributed to Lassi Lehtisyrjä.

3 recordsLinked to original sources

Cryogenic wafer probing below one Kelvin: Characterization of normal-metal Coulomb blockade thermometers at wafer scale

Coulomb blockade thermometers (CBTs) have attracted more interest in recent years, as the demand for sub-one Kelvin thermometry has increased, especially due to the prevalence of dilution refrigerators in research and applications in quantum technology. CBTs can be operated both as a primary thermometer, requiring no prior calibration, or as a simple resistance thermometer in the secondary mode after calibration. As new scalable fabrication processes for quantum devices and cryogenic electronics are being developed, cryogenic wafer characterization methods must also scale up to provide statistical data on device parameters. Currently, characterization throughput of cryogenic devices is limited by the turnover time and sample capacity of traditional cryostats, where a measurement cycle for only a few devices can take several days. In this work, we demonstrate wafer-scale cryogenic characterization of a recently developed TiW/Al-AlOx/TiW normal-metal tunnel junction technology using CBTs. Measurements performed in a 300 mm cryogenic wafer prober (CWP) show on-chip electron temperatures below 700 mK across a full 150 mm wafer, as determined by primary thermometry. These results establish wafer-level testing below 1 K as a viable approach for large-scale cryogenic characterization of electrical devices, opening a pathway toward high-throughput screening of quantum devices and direct wafer-scale characterization of aluminum-based superconducting circuits.

cond-mat.mes-hall↗

A scalable non-superconducting tunnel junction technology

Tunnel junctions are one of the key elements of chip-scale microsystems serving various technologies from classical microelectronics to quantum information. Aluminium and its oxide (AlOx) have dominated cryogenic tunnel junction technology for decades due to the high quality of AlOx barriers and Al superconducting properties below 1.2 K. However, many applications require non-superconducting junctions, either standalone or in combination with superconducting technology, motivating efforts to suppress Al superconductivity through magnetic fields, doping, or proximity effects -- approaches that so far suffered from integration compatibility and scalability issues. Here, we present a CMOS-compatible normal-metal tunnel junction technology based on TiW alloy and AlOx barriers. We demonstrate wafer-scale fabrication of TiW/Al-AlOx/TiW junctions and validate their performance in Coulomb blockade thermometers operating down to 20 mK, confirming robust normal-state behavior. This TiW-based architecture offers a scalable solution for non-superconducting tunnel junctions across a broad temperature range, enabling integration into advanced cryogenic, quantum and nanoelectronic chip-level systems.

cond-mat.mes-hall↗

Thermal resistance in superconducting flip-chip assemblies

Cryogenic microsystems that utilize different 3D integration techniques are being actively developed, e.g., for the needs of quantum technologies. 3D integration can introduce opportunities and challenges to the thermal management of low temperature devices. In this work, we investigate sub-1 K inter-chip thermal resistance of a flip-chip bonded assembly, where two silicon chips are interconnected by compression bonding via indium bumps. The total thermal contact area between the chips is 0.306 mm$^2$ and we find that the temperature dependence of the inter-chip thermal resistance follows the power law of $αT^{-3}$, with $α= 7.7-15.4$ K$^4$$μ$m$^2$/nW. The $T^{-3}$ relation indicates phononic interfacial thermal resistance, which is supported by the vanishing contribution of the electrons to the thermal conduction, due to the superconducting interconnections. Such a thermal resistance value can introduce a thermalization bottleneck in particular at cryogenic temperatures. This can be detrimental for some applications, yet it can also be harnessed. We provide an example of both cases by estimating the parasitic overheating of a cryogenic flip-chip assembly operated under various heat loads as well as simulate the performance of solid-state junction microrefrigerators utilizing the observed thermal isolation.

physics.app-ph↗