arXiv subjects

Lawrence Pileggi

Publications and source records attributed to Lawrence Pileggi.

7 recordsLinked to original sources

arXiv2026

Unifying Power Flow and Electromagnetic Transient Modeling

Grid tools are separated by timescales: steady-state analysis is performed by power flow (PF), whereas the fastest dynamics are captured by electromagnetic transient (EMT) simulation. Although operating at varying timescales, different tools should produce consistent results when analyzing the same grid conditions. However, the PF steady-state solution does not match the time-to-infinity EMT response. This mismatch exists because simplified device models in PF are inconsistent with the "ground truth" EMT models derived from first principles. As inverter-based resources (IBRs) and data centers strip away inertia and operating reserves, approximations used in PF risk grid security by missing violations. To address this, we introduce a steady-state framework that uses full-physics EMT models for high-fidelity steady-state grid analysis. The challenge lies in systematically formulating algebraic frequency-domain representations of dynamic power devices that are naturally described in state-space form. Our tool, SALT (Steady-state After Last Transients), constructs steady-state representations that exactly capture grid device physics when embedded into transmission networks. The approach exploits the structural properties of power device models and the single-harmonic, balanced nature of the transmission system. Results demonstrate SALT achieves EMT steady-state accuracy while delivering a 1x10^6 times speedup. We demonstrate that SALT can capture security threats in contingency scenarios without exception --- whereas PF-based analyses reported 75% fewer rated line violations, 18% fewer Q-limit violations, and 7% fewer voltage violations.

eess.SY↗

arXiv2026

Security Analysis of Universal Circuits as a Mechanism for Hardware Obfuscation

Universal Circuits (UCs) offer a promising approach to hardware Intellectual Property (IP) obfuscation, leveraging cryptographic principles to hide both structure and function in a programmable logic fabric. Their adaptability makes them especially suitable for the globalized Integrated Circuit (IC) supply chain, where security against threats like reverse engineering is crucial. Despite the potential, UC security remains largely unexplored. This work evaluates UC security against state-of-the-art oracle-guided (OG) and oracle-less (OL) attacks. Results show near-random success rates (approx 50%) for OG attacks whereas OL attacks display minimal structural leakage. Collectively, these findings confirm the feasibility of UCs for IP protection.

cs.CR↗

arXiv2025

Sparsity-exploiting Gaussian Process for Robust Transient Learning of Power System Dynamics

Advances in leveraging Gaussian processes (GP) have enabled learning and inferring dynamic grid behavior from scarce PMU measurements. However, real measurements can be corrupted by various random and targeted threats, leading to inaccurate and meaningless results. This paper develops robust transient learning to overcome this challenge by exploiting the sparse corruption patterns in the data flow. Specifically, we integrate sparse optimization with method of moments (MoM) to make learning robust to a sparse distribution of data corruptions; then, we optimize sparse weights to identify corrupted meter locations. To improve inference speed on large-scale systems, we further adopt K-medoid clustering of locations to develop dimension reduction (DR) and aggregate representation (AR) heuristics. Experimental results demonstrate robustness against random large errors, targeted false data injections, and local PMU clock drifts. On a 1354-bus system, inference turns out to be 18x faster using DR and 400x faster when further combined with AR heuristics.

eess.SY↗

arXiv2021

Quantifying the Efficacy of Logic Locking Methods

The outsourced manufacturing of integrated circuits has increased the risk of intellectual property theft. In response, logic locking techniques have been developed for protecting designs by adding programmable elements to the circuit. These techniques differ significantly in both overhead and resistance to various attacks, leaving designers unable to discern their efficacy. To overcome this critical impediment for the adoption of logic locking, we propose two metrics, key corruption and minimum corruption, that capture the goals of locking under different attack scenarios. We develop a flow for approximating these metrics on generic locked circuits and evaluate several locking techniques.

cs.CR↗

arXiv2020

Modeling Techniques for Logic Locking

Logic locking is a method to prevent intellectual property (IP) piracy. However, under a reasonable attack model, SAT-based methods have proven to be powerful in obtaining the secret key. In response, many locking techniques have been developed to specifically resist this form of attack. In this paper, we demonstrate two SAT modeling techniques that can provide many orders of magnitude speed up in discovering the correct key. Specifically, we consider relaxed encodings and symmetry breaking. To demonstrate their impact, we model and attack a state-of-the-art logic locking technique, Full-Lock. We show that circuits previously unbreakable within 15 days of run time can be solved in seconds. Consequently, in assessing the strength of any given locking, it is imperative that these modeling techniques be considered. To remedy this vulnerability in the considered locking technique, we demonstrate an extended version, logic-enhanced Banyan locking, that is resistant to our proposed modeling techniques.

cs.CR↗

arXiv2020

Latch-Based Logic Locking

Globalization of IC manufacturing has led to increased security concerns, notably IP theft. Several logic locking techniques have been developed for protecting designs, but they typically display very large overhead, and are generally susceptible to deciphering attacks. In this paper, we propose latch-based logic locking, which manipulates both the flow of data and logic in the design. This method converts an interconnected subset of existing flip-flops to pairs of latches with programmable phase. In tandem, decoy latches and logic are added, inhibiting an attacker from determining the actual design functionality. To validate this technique, we developed and verified a locking insertion flow, analyzed PPA and ATPG overhead on benchmark circuits and industry cores, extended existing attacks to account for the technique, and taped out a demonstration chip. Importantly, we show that the design overhead with this approach is significantly less than with previous logic locking schemes, while resisting model checker-based, oracle-driven attacks. With minimal delay overhead, large numbers of decoy latches can be added, cheaply increasing attack resistance.

cs.CR↗

arXiv2020

Securing Digital Systems via Split-Chip Obfuscation

Security is an important facet of integrated circuit design for many applications. IP privacy and Trojan insertion are growing threats as circuit fabrication in advanced nodes almost inevitably relies on untrusted foundries. A proposed solution is Split-Chip Obfuscation that uses a combination trusted and untrusted IC fabrication scheme. By utilizing two CMOS processes, a system is endowed with the stronger security guaranties of a trusted legacy node while also leveraging the performance and density of an advanced untrusted node. Critical to the effectiveness of Split-Chip Obfuscation is finding an optimum partitioning of a system between the two ICs. In this paper, we develop a design flow for the Split-Chip Obfuscation scheme, defining the essential system metrics and creating a tool to rapidly assess the large design space. We demonstrate the concept of such a tool and show its application on an example SoC.

cs.CR↗