arXiv subjects

Leonard M. Johnson

Publications and source records attributed to Leonard M. Johnson.

6 recordsLinked to original sources

arXiv2023

Extremely Large Area (88 mm X 88 mm) Superconducting Integrated Circuit (ELASIC)

Superconducting integrated circuit (SIC) is a promising "beyond-CMOS" device technology enables speed-of-light, nearly lossless communications to advance cryogenic (4 K or lower) computing. However, the lack of large-area superconducting IC has hindered the development of scalable practical systems. Herein, we describe a novel approach to interconnect 16 high-resolution deep UV (DUV EX4, 248 nm lithography) full reticle circuits to fabricate an extremely large (88mm X 88 mm) area superconducting integrated circuit (ELASIC). The fabrication process starts by interconnecting four high-resolution DUV EX4 (22 mm X 22 mm) full reticles using a single large-field (44 mm X 44 mm) I-line (365 nm lithography) reticle, followed by I-line reticle stitching at the boundaries of 44 mm X 44 mm fields to fabricate the complete ELASIC field (88 mm X 88 mm). The ELASIC demonstrated a 2X-12X reduction in circuit features and maintained high-stitched line superconducting critical currents. We examined quantum flux parametron (QFP) circuits to demonstrate the viability of common active components used for data buffering and transmission. Considering that no stitching requirement for high-resolution EX4 DUV reticles is employed, the present fabrication process has the potential to advance the scaling of superconducting quantum devices.

cond-mat.supr-con↗

arXiv2023

Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers

To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of $10^8$ Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted Nb/Al-AlOx/Nb JJs and kinetic inductors. The process has a layer of JJs, a layer of resistors, and 10 fully planarized superconducting layers: 8 Nb layers and 2 layers of high kinetic inductance materials, Mo$_2$N and NbN, with sheet inductance of 8 pH/sq and 3 pH/sq, respectively. NbN films were deposited by two methods: with $T_c$=15.5 K by reactive sputtering of a Nb target in Ar+N$_2$ mixture; with $T_c$ in the range from 9 K to 13 K by plasma-enhanced chemical vapor deposition (PECVD) using Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of NbN was investigated to obtain conformal deposition and filling narrow trenches and vias with high depth-to-width ratios, which was not possible to achieve using sputtering and other physical vapor deposition (PVD) methods at temperatures below $200 ^oC$ required to prevent degradation of Nb/Al-AlOx/Nb junctions. Nb layers with 200 nm thickness are used in the process layer stack as ground planes to maintain a high level of interlayer shielding and low intralayer mutual coupling, for passive transmission lines with wave impedances matching impedances of JJs, typically <=50 $Ω$, and for low-value inductors. NbN and NbN/Nb bilayer are used for cell inductors. Using NbN/Nb bilayers and individual pattering of both layers to form inductors allowed us to minimize parasitic kinetic inductance associated with interlayer vias and connections to JJs as well as to increase critical currents of the vias. Fabrication details and results of electrical characterization of NbN films, wires, and vias, and comparison with Nb properties are given.

cond-mat.supr-con↗

arXiv2019

Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions

We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional Superconductor-Insulator-Superconductor (SIS) Nb/Al/AlO_x/Nb junctions with the same or different Josephson critical current densities, J_c. The process also allows integration of high-J_c Superconductor-Ferromagnet-Superconductor (SFS) or SFS'S JJs on the first junction layer with Nb/Al/AlO_x/Nb trilayer junctions on the second junction layer, or vice versa. In the present node, the SFS trilayer, Nb/Ni/Nb is placed below the standard SIS trilayer and separated by one niobium wiring layer. The main purpose of integrating the SFS and SIS junction layers is to provide compact π-phase shifters in logic cells of superconductor digital circuits and random access memories, and thereby increase the integration scale and functional density of superconductor electronics. The current node of the two-junction-layer process has six planarized niobium layers, two layers of resistors, and 350-nm minimum feature size. The target Josephson critical current densities for the SIS junctions are 100 μA/μm^2 and 200 μA/μm^2. We present the salient features of the new process, fabrication details, and characterization results on two layers of Josephson junctions integrated into one process, both for the conventional and π-junctions.

cond-mat.supr-con↗

arXiv2017

Developments Toward a 250-nm, Fully Planarized Fabrication Process With Ten Superconducting Layers And Self-Shunted Josephson Junctions

We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 μm made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.

cond-mat.supr-con↗

arXiv2014

Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process with 8 Niobium Layers

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90-degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities > 10^6 Josephson junctions per cm^2 are discussed.

cond-mat.supr-con↗

arXiv2014

Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al-AlOx/Nb Josephson Junctions for VLSI Circuits

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO$_2$ interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, $I_c$, normal-state conductance, $G_N$, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, $J_c$, from 10 kA/$cm^2$ to 50 kA/$cm^2$ where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The $G_N$ and $I_c$ spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. $I_c$ and $G_N$ spreads from 0.8% to 3% have been obtained for JJs with sizes from 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > $10^6$ JJ/$cm^2$ and 193-nm photolithography for JJ definition are discussed.

cond-mat.supr-con↗