arXiv subjects

Li Du

Publications and source records attributed to Li Du.

101 records · Page 6Linked to original sources

arXiv2019

Modeling Event Background for If-Then Commonsense Reasoning Using Context-aware Variational Autoencoder

Understanding event and event-centered commonsense reasoning are crucial for natural language processing (NLP). Given an observed event, it is trivial for human to infer its intents and effects, while this type of If-Then reasoning still remains challenging for NLP systems. To facilitate this, a If-Then commonsense reasoning dataset Atomic is proposed, together with an RNN-based Seq2Seq model to conduct such reasoning. However, two fundamental problems still need to be addressed: first, the intents of an event may be multiple, while the generations of RNN-based Seq2Seq models are always semantically close; second, external knowledge of the event background may be necessary for understanding events and conducting the If-Then reasoning. To address these issues, we propose a novel context-aware variational autoencoder effectively learning event background information to guide the If-Then reasoning. Experimental results show that our approach improves the accuracy and diversity of inferences compared with state-of-the-art baseline methods.

cs.CL↗

arXiv2019

Training Deep Neural Networks Using Posit Number System

With the increasing size of Deep Neural Network (DNN) models, the high memory space requirements and computational complexity have become an obstacle for efficient DNN implementations. To ease this problem, using reduced-precision representations for DNN training and inference has attracted many interests from researchers. This paper first proposes a methodology for training DNNs with the posit arithmetic, a type- 3 universal number (Unum) format that is similar to the floating point(FP) but has reduced precision. A warm-up training strategy and layer-wise scaling factors are adopted to stabilize training and fit the dynamic range of DNN parameters. With the proposed training methodology, we demonstrate the first successful training of DNN models on ImageNet image classification task in 16 bits posit with no accuracy loss. Then, an efficient hardware architecture for the posit multiply-and-accumulate operation is also proposed, which can achieve significant improvement in energy efficiency than traditional floating-point implementations. The proposed design is helpful for future low-power DNN training accelerators.

cs.LG↗

arXiv2019

Enhancing the capture velocity of a Dy magneto-optical trap with two-stage slowing

Magneto-optical traps (MOTs) based on the $626\;{\rm nm}$, $136\;{\rm kHz}$-wide intercombination line of Dy, which has an attractively low Doppler temperature of $3.3\;μ{\rm K}$, have been implemented in a growing number of experiments over the last several years. A challenge in loading these MOTs comes from their low capture velocities. Slowed atomic beams can spread out significantly during free-flight from the Zeeman slower to the MOT position, reducing the fraction of the beam captured by the MOT. Here we apply, for the first time in a Dy experiment, a scheme for enhancing the loading rate of the MOT wherein atoms are Zeeman-slowed to a final velocity larger than the MOT's capture velocity, and then undergo a final stage of slowing by a pair of near-detuned beams addressing the $421\;{\rm nm}$ transition directly in front of the MOT. By reducing the free-flight time of the Zeeman-slowed atomic beam, we greatly enhance the slowed flux delivered to the MOT, leading to more than an order of magnitude enhancement in the final MOT population.

cond-mat.quant-gas↗

arXiv2018

An Analog Neural Network Computing Engine using CMOS-Compatible Charge-Trap-Transistor (CTT)

An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces. Through implementing the sequential analog fabric (SAF), the engine mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28nm CMOS technology and occupied 0.68mm2. The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem -- classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.

cs.ET↗

arXiv2018

Comment on "A Nonholonomic Model of the Paul Trap"

A recent article by Borisov et al. [Regular and Chaotic Dynamics 23.3 (2018): 339-354.] studies the motion of a rigid ball in a rotating-saddle trap. The authors claim that they derive a new equation of motion from the Lagrangian formalism, which is different from the one we obtained from the Newtonian formalism in our recent work [American Journal of Physics 85.11 (2017): 821-829.]. We show here that these two equations of motion are the same. In addition, besides the reduced spin frequency and the moment of inertia coefficient, the stability condition given by the article is independent of the ball radius---this result is incorrect. The mistake is due to the fact that the center of mass and the contact point are not distinguished in the explicit expression of the local normal vector.

physics.class-ph↗

arXiv2017

Confining rigid balls by mimicking quadrupole ion trapping

The rotating saddle not only is an interesting system that is able to trap a ball near its saddle point, but can also intuitively illustrate the operating principles of quadrupole ion traps in modern physics. Unlike the conventional models based on the mass-point approximation, we study the stability of a ball in a rotating-saddle trap using rigid-body dynamics. The stabilization condition of the system is theoretically derived and subsequently verified by experiments. The results are compared with the previous mass-point model, giving large discrepancy as the curvature of the ball is comparable to that of the saddle. We also point out that the spin angular velocity of the ball is analogous to the cyclotron frequency of ions in an external magnetic field utilized in many prevailing ion-trapping schemes.

physics.class-ph↗

arXiv2017

A Streaming Accelerator for Deep Convolutional Neural Networks with Image and Feature Decomposition for Resource-limited System Applications

Deep convolutional neural networks (CNN) are widely used in modern artificial intelligence (AI) and smart vision systems but also limited by computation latency, throughput, and energy efficiency on a resource-limited scenario, such as mobile devices, internet of things (IoT), unmanned aerial vehicles (UAV), and so on. A hardware streaming architecture is proposed to accelerate convolution and pooling computations for state-of-the-art deep CNNs. It is optimized for energy efficiency by maximizing local data reuse to reduce off-chip DRAM data access. In addition, image and feature decomposition techniques are introduced to optimize memory access pattern for an arbitrary size of image and number of features within limited on-chip SRAM capacity. A prototype accelerator was implemented in TSMC 65 nm CMOS technology with 2.3 mm x 0.8 mm core area, which achieves 144 GOPS peak throughput and 0.8 TOPS/W peak energy efficiency.

cs.AR↗

arXiv2017

A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the internet of things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution window size. In addition, max pooling function can be computed in parallel with convolution by using separate pooling unit, thus achieving throughput improvement. A prototype accelerator was implemented in TSMC 65nm technology with a core size of 5mm2. The accelerator can support major CNNs and achieve 152GOPS peak throughput and 434GOPS/W energy efficiency at 350mW, making it a promising hardware accelerator for intelligent IoT devices.

cs.CV↗

arXiv2017

A/D Converter Architectures for Energy-Efficient Vision Processor

AI applications have emerged in current world. Among AI applications, computer-vision (CV) related applications have attracted high interest. Hardware implementation of CV processors necessitates a high performance but low-power image detector. The key to energy-efficiency work lies in analog-digital converting, where output of imaging detectors is transferred to digital domain and CV algorithms can be performed on data. In this paper, analog-digital converter architectures are compared, and an example ADC design is proposed which achieves both good performance and low power consumption.

cs.ET↗

arXiv2017

1.5 bit-per-stage 8-bit Pipelined CMOS A/D Converter for Neuromophic Vision Processor

Neuromorphic vision processor is an electronic implementation of vision algorithm processor on semiconductor. To image the world, a low-power CMOS image sensor array is required in the vision processor. The image sensor array is typically formed through photo diodes and analog to digital converter (ADC). To achieve low power acquisition, a low-power mid-resolution ADC is necessary. In this paper, a 1.8V, 8-bit, 166MS/s pipelined ADC was proposed in a 0.18 um CMOS technology. The ADC used operational amplifier sharing architecture to reduce power consumption and achieved maximum DNL of 0.24 LSB, maximum INL of 0.35 LSB, at a power consumption of 38.9mW. When input frequency is 10.4MHz, it achieved an SNDR 45.9dB, SFDR 50dB, and an ENOB of 7.33 bit.

cs.AR↗

arXiv2016

An Overview of Mobile Capacitive Touch Technologies Trends

Touch sensing, as a major human/machine interface, is widely used in various commercial products such as smart watches, mobile phones, tablets and TVs. State-of-the-art touch detections are mainly based on mutual capacitive sensing, which requires necessary contact-touch, limiting the mobile user experience. Recently, remote gesture sensing is widely reported in both academy and industry as it can provide additional user-experience for mobile interface. The capacitive remote gesture sensing is mainly based on detecting self-capacitance, achieving high resolution through eliminating the parasitic mutual capacitance. In this work, we overview the different generations of touchscreen technology, comparing the touch and remote gesture sensing technologies difference. In addition, different remote gesture sensing technologies are also compared. The limitations and potentials of different topologies are discussed and a final conclusion about the technology trends is summarized in the end.

cs.ET↗