arXiv subjects

Loris Mendolia

Publications and source records attributed to Loris Mendolia.

3 recordsLinked to original sources

arXiv2026

Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations

Always-on AI applications, from environmental sensors to biomedical implants, require ultra-low power consumption. Analog circuits offer a path to sub-microwatt inference, yet existing analog implementations are limited to feedforward architectures: extending them to recurrent dynamics has been considered impractical due to noise accumulation through temporal feedback. We demonstrate that this barrier can be overcome through hardware-software co-design. Specifically, we identify that Bistable Memory Recurrent Units (BMRUs), a class of Recurrent Neural Networks (RNNs) with discrete-valued outputs and hysteretic dynamics, admit an ultra-low power current-mode analog implementation which we design from first principles. The resulting circuit establishes a one-to-one correspondence between each learned parameter and a circuit element. The discrete outputs suppress analog noise by at least 20-fold at each cell boundary, breaking the noise accumulation that prevents analog recurrence. We reformulate BMRUs for first-quadrant operation with fixed thresholds, enabling the direct correspondence while preserving expressivity and trainability. Transistor-level simulations in 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) show near-perfect agreement between software predictions and circuit-level behavior, with the software model thereby serving as a high-fidelity simulator of the physical hardware at low computational cost. We leverage this fidelity to conduct large-scale noise immunity and power scaling analyses: the power cost of adding recurrence scales linearly with state dimension, while the feedforward layers dominating total power scale quadratically, meaning recurrence is added at linear marginal cost relative to the feedforward backbone. End-to-end keyword spotting achieves sub-microwatt inference at the RNN core.

cs.AR↗

arXiv2026

A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology

This work introduces a fully tunable, ultra-low power unipolar memory cell inspired by the Schmitt-trigger comparator and designed in CMOS using only nine transistors. The proposed circuit operates entirely in the current domain and exploits a novel feedback configuration between two interdependent Heaviside-like thresholding elements to produce tunable bistable switching behavior. Its three key parameters-threshold current, hysteresis width, and output gain-are independently tunable via programmable bias currents, enabling flexibility across diverse analog computing applications. Unlike prior Schmitt-trigger designs, it simultaneously achieves current-mode operation, nanowatt-range power consumption, temperature stability, and full tunability, solely using standard MOSFET elements. Schematic-level simulations in a 180 nm CMOS process confirm robust hysteresis and resilience to device mismatch. Building on this circuit, we develop a complete family of spike-based logic gates using three-level current encoding, where the bistable memory retains the polarity of the last spike on each input indefinitely, enabling asynchronous logic operations without temporal windowing or refresh mechanisms. The same circuit also serves as the primitive for Bistable Memory Recurrent Units in analog neural networks, where the quantized hidden states provide inherent noise immunity. Together, these capabilities position the design as a versatile building block for next-generation neuromorphic processors integrating memory, logic, and recurrent computation.

eess.SP↗

arXiv2025

A Neuromodulable Current-Mode Silicon Neuron for Robust and Adaptive Neuromorphic Systems

Neuromorphic engineering makes use of mixed-signal analog and digital circuits to directly emulate the computational principles of biological brains. Such electronic systems offer a high degree of adaptability, robustness, and energy efficiency across a wide range of tasks, from edge computing to robotics. Within this context, we investigate a key feature of biological neurons: their ability to carry out robust and reliable computation by adapting their input responses and spiking patterns to context through neuromodulation. Achieving analogous levels of robustness and adaptation in neuromorphic circuits through modulatory mechanisms is a largely unexplored path. We present a novel current-mode neuron design that supports robust neuromodulation with minimal model complexity, compatible with standard CMOS technologies. We first introduce a mathematical model of the circuit and provide tools to analyze and tune the neuron behavior; we then demonstrate both theoretically and experimentally the biologically plausible neuromodulation adaptation capabilities of the circuit over a wide range of parameters. All theoretical predictions were verified in experiments on a low-power 180 nm CMOS implementation of the proposed neuron circuit. Due to the analog underlying feedback structure, the proposed adaptive neuromodulable neuron exhibits a high degree of robustness, flexibility, and scalability across operating ranges of currents and temperatures, making it a perfect candidate for real-world neuromorphic applications.

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