arXiv subjects

Luke Theogarajan

Publications and source records attributed to Luke Theogarajan.

8 recordsLinked to original sources

arXiv2025

Analyzing Parametric Oscillator Ising Machines through the Kuramoto Lens

Networks of coupled nonlinear oscillators are emerging as powerful physical platforms for implementing Ising machines. Yet the relationship between parametric-oscillator implementations and traditional oscillator-based Ising machines remains underexplored. In this work, we develop a Kuramoto-style, canonical phase description of parametric oscillator Ising machines by starting from the Stuart-Landau oscillator model -- the canonical normal form near a Hopf bifurcation, and a natural reduced description for many parametric oscillator implementations such as the degenerate optical parametric oscillator (DOPO) among others. The resulting phase dynamics combine the usual phase-difference coupling observed in the standard Kuramoto model along with an intrinsic phase sum term that is generated when conjugate coupling is considered. Moreover, our formulation helps explain why explicit second-harmonic driving is unnecessary in parametric oscillators and also reveals how quasi-steady amplitude heterogeneity scales the original strength of the spin interaction with potentially adverse impacts on the solution quality. Our work helps develop a unifying view of the oscillator-based approach to designing Ising machines.

eess.SY↗

arXiv2025

The Gaussian-Multinoulli Restricted Boltzmann Machine: A Potts Model Extension of the GRBM

Many real-world tasks, from associative memory to symbolic reasoning, benefit from discrete, structured representations that standard continuous latent models can struggle to express. We introduce the Gaussian-Multinoulli Restricted Boltzmann Machine (GM-RBM), a generative energy-based model that extends the Gaussian-Bernoulli RBM (GB-RBM) by replacing binary hidden units with q-state categorical (Potts) units, yielding a richer latent state space for multivalued concepts. We provide a self-contained derivation of the energy, conditional distributions, and learning rules, and detail practical training choices (contrastive divergence with temperature annealing and intra-slot diversity constraints) that avoid state collapse. To separate architectural effects from sheer latent capacity, we evaluate under both capacity-matched and parameter-matched setups, comparing GM-RBM with GB-RBM configured to have the same number of possible latent assignments. On analogical recall and structured memory benchmarks, GM-RBM achieves competitive, and in several regimes improved, recall at equal capacity with comparable training cost, despite using only Gibbs updates. The discrete q-ary formulation is also amenable to efficient implementation. These results clarify when categorical hidden units provide a simple, scalable alternative to binary latents for discrete inference within tractable RBMs.

cs.LG↗

arXiv2025

A CMOS Probabilistic Computing Chip With In-situ hardware Aware Learning

This paper demonstrates a probabilistic bit physics inspired solver with 440 spins configured in a Chimera graph, occupying an area of 0.44 mm^2. Area efficiency is maximized through a current-mode implementation of the neuron update circuit, standard cell design for analog blocks pitch-matched to digital blocks, and a shared power supply for both digital and analog components. Process variation related mismatches introduced by this approach are effectively mitigated using a hardware aware contrastive divergence algorithm during training. We validate the chip's ability to perform probabilistic computing tasks such as modeling logic gates and full adders, as well as optimization tasks such as MaxCut, demonstrating its potential for AI and machine learning applications.

cs.AR↗

arXiv2023

A full-stack view of probabilistic computing with p-bits: devices, architectures and algorithms

The transistor celebrated its 75${}^\text{th}$ birthday in 2022. The continued scaling of the transistor defined by Moore's Law continues, albeit at a slower pace. Meanwhile, computing demands and energy consumption required by modern artificial intelligence (AI) algorithms have skyrocketed. As an alternative to scaling transistors for general-purpose computing, the integration of transistors with unconventional technologies has emerged as a promising path for domain-specific computing. In this article, we provide a full-stack review of probabilistic computing with p-bits as a representative example of the energy-efficient and domain-specific computing movement. We argue that p-bits could be used to build energy-efficient probabilistic systems, tailored for probabilistic algorithms and applications. From hardware, architecture, and algorithmic perspectives, we outline the main applications of probabilistic computers ranging from probabilistic machine learning and AI to combinatorial optimization and quantum simulation. Combining emerging nanodevices with the existing CMOS ecosystem will lead to probabilistic computers with orders of magnitude improvements in energy efficiency and probabilistic sampling, potentially unlocking previously unexplored regimes for powerful probabilistic algorithms.

cs.ET↗

arXiv2022

CMOS-compatible Ising and Potts Annealing Using Single Photon Avalanche Diodes

Massively parallel annealing processors may offer superior performance for a wide range of sampling and optimization problems. A key component dictating the size of these processors is the neuron update circuit, ideally implemented using special stochastic nanodevices. We leverage photon statistics using single photon avalanche diodes (SPADs) and temporal filtering to generate stochastic states. This method is a powerful alternative offering unique features not currently seen in annealing processors: the ability to continuously control the computational temperature and the seamless extension to the Potts model, a $n$-state generalization of the two-state Ising model. SPADs also offer a considerable practical advantage since they are readily manufacturable in current standard CMOS processes. As a first step towards realizing a CMOS SPAD-based annealer, we have designed Ising and Potts models driven by an array of discrete SPADs and show they accurately sample from their theoretical distributions.

cs.ET↗

arXiv2022

Massively Parallel Probabilistic Computing with Sparse Ising Machines

Inspired by the developments in quantum computing, building domain-specific classical hardware to solve computationally hard problems has received increasing attention. Here, by introducing systematic sparsification techniques, we demonstrate a massively parallel architecture: the sparse Ising Machine (sIM). Exploiting sparsity, sIM achieves ideal parallelism: its key figure of merit - flips per second - scales linearly with the number of probabilistic bits (p-bit) in the system. This makes sIM up to 6 orders of magnitude faster than a CPU implementing standard Gibbs sampling. Compared to optimized implementations in TPUs and GPUs, sIM delivers 5-18x speedup in sampling. In benchmark problems such as integer factorization, sIM can reliably factor semiprimes up to 32-bits, far larger than previous attempts from D-Wave and other probabilistic solvers. Strikingly, sIM beats competition-winning SAT solvers (by 4-700x in runtime to reach 95% accuracy) in solving 3SAT problems. Even when sampling is made inexact using faster clocks, sIM can find the correct ground state with further speedup. The problem encoding and sparsification techniques we introduce can be applied to other Ising Machines (classical and quantum) and the architecture we present can be used for scaling the demonstrated 5,000-10,000 p-bits to 1,000,000 or more through analog CMOS or nanodevices.

cs.ET↗

arXiv2021

A 125$μ$W 8kS/s Sub-pA Area-Efficient Current Sensing 45nm CMOS ADC for Biosensing

This paper presents a 125$μ$W, area efficient (0.042mm2) 81dB DR, 8kS/s current sensing ADC in 45nm CMOS capable of sensing sub-pA currents. Our approach combines the transimpedance amplifier (TIA) and ADC into a unified structure by folding a low-noise capacitive TIA into the first stage integrator of a 2nd order Delta-Sigma modulator. The dominant DAC feedback noise is mitigated by utilizing current scaling via slope modification by an integrator and differentiator pair.

eess.SP↗

arXiv2017

An Integrated-Photonics Optical-Frequency Synthesizer

Integrated-photonics microchips now enable a range of advanced functionalities for high-coherence applications such as data transmission, highly optimized physical sensors, and harnessing quantum states, but with cost, efficiency, and portability much beyond tabletop experiments. Through high-volume semiconductor processing built around advanced materials there exists an opportunity for integrated devices to impact applications cutting across disciplines of basic science and technology. Here we show how to synthesize the absolute frequency of a lightwave signal, using integrated photonics to implement lasers, system interconnects, and nonlinear frequency comb generation. The laser frequency output of our synthesizer is programmed by a microwave clock across 4 THz near 1550 nm with 1 Hz resolution and traceability to the SI second. This is accomplished with a heterogeneously integrated III/V-Si tunable laser, which is guided by dual dissipative-Kerr-soliton frequency combs fabricated on silicon chips. Through out-of-loop measurements of the phase-coherent, microwave-to-optical link, we verify that the fractional-frequency instability of the integrated photonics synthesizer matches the $7.0*10^{-13}$ reference-clock instability for a 1 second acquisition, and constrain any synthesis error to $7.7*10^{-15}$ while stepping the synthesizer across the telecommunication C band. Any application of an optical frequency source would be enabled by the precision optical synthesis presented here. Building on the ubiquitous capability in the microwave domain, our results demonstrate a first path to synthesis with integrated photonics, leveraging low-cost, low-power, and compact features that will be critical for its widespread use.

physics.app-ph↗