arXiv subjects

M Mahmudul Hasan Sajeeb

Publications and source records attributed to M Mahmudul Hasan Sajeeb.

5 recordsLinked to original sources

arXiv2026

A Single-Inductor N:1 Resonant Switched-Capacitor Ladder Converter with Efficient Continuous Voltage Conversion Capability

This paper presents an N:1 resonant switched-capacitor (ReSC) ladder converter of an output voltage that can be regulated continuously below the native N:1 resonant ratio while maintaining high efficiency. The topology can be generalized to any N-to-1 dc-dc conversion application while requiring only a single inductor. Efficient wide-range voltage regulation is realized by operating the bottom stack of the ReSC switches as diodes to maintain their switching always in phase with the inductor current, and hence, circumvent circulating currents that increase the inductor RMS current and ohmic losses under frequency control. A theoretical model has been developed to predict the output voltage and efficiency of the converter, with simulation results confirming its accuracy for N = 1, 2, and 4. A hardware prototype on a printed circuit board is developed to validate the performance of the proposed frequency-controlled regulation scheme. The prototype achieves a peak efficiency of 97% (94.3%) with a load of 30Ohms (resp. 6Ohms) and an efficiency >90% while generating a 9V USB-compatible voltage from a 40V-to-60V input. The measurement results match the model predictions within 0.63% accuracy.

eess.SY↗

arXiv2026

Probabilistic Computers for MIMO Detection: From Sparsification to 2D Parallel Tempering

Probabilistic computers built from p-bits offer a promising path for combinatorial optimization, but the dense connectivity required by real-world problems scales poorly in hardware. Here, we address this through graph sparsification with auxiliary copy variables and demonstrate two fully on-chip parallel tempering solvers on an FPGA. Targeting MIMO detection, a dense, NP-hard problem central to wireless communications, we first fit 11 temperature replicas of a 128-node sparsified system (1,408 p-bits) on-chip and achieve bit error rates significantly below conventional linear detectors on $64 \times 64$ BPSK MIMO. We report complete end-to-end solution times of 3~ms per instance, including all loading, sampling, readout, and verification overheads. ASIC projections in 7~nm technology indicate 103~MHz operation at 285.8~mW, suggesting that massive parallelism across multiple chips could approach the throughput demands of next-generation wireless systems. Sparsification, however, introduces a sharp sensitivity to the copy-constraint strength $P$ that requires manual tuning. To eliminate this bottleneck, we utilize Two-Dimensional Parallel Tempering (2D-PT), which exchanges replicas across both temperature ($β$) and constraint ($P$) dimensions. On Sherrington--Kirkpatrick spin glasses, 2D-PT converges roughly $250\times$ faster than optimally tuned 1D-PT, and on $128 \times 128$ MIMO it reaches zero bit errors at high SNR where 1D-PT exhibits an error floor. We further validate 2D-PT entirely on-chip with 54 replicas (1,728 p-bits) on a $16 \times 16$ MIMO instance, where it tracks the maximum-likelihood bound in just 50 Monte Carlo steps -- $10\times$ fewer than 1D-PT -- at projected 111~MHz and 124~mW in 7~nm. Together, these results establish an on-chip p-bit architecture and a scalable, tuning-free algorithmic framework for dense combinatorial optimization.

cs.ET↗

arXiv2025

Two-dimensional Parallel Tempering for Constrained Optimization

Sampling Boltzmann probability distributions plays a key role in machine learning and optimization, motivating the design of hardware accelerators such as Ising machines. While the Ising model can in principle encode arbitrary optimization problems, practical implementations are often hindered by soft constraints that either slow down mixing when too strong, or fail to enforce feasibility when too weak. We introduce a two-dimensional extension of the powerful parallel tempering algorithm (PT) that addresses this challenge by adding a second dimension of replicas interpolating the penalty strengths. This scheme ensures constraint satisfaction in the final replicas, analogous to low-energy states at low temperature. The resulting two-dimensional parallel tempering algorithm (2D-PT) improves mixing in heavily constrained replicas and eliminates the need to explicitly tune the penalty strength. In a representative example of graph sparsification with copy constraints, 2D-PT achieves near-ideal mixing, with Kullback-Leibler divergence decaying as O(1/t). When applied to sparsified Wishart instances, 2D-PT yields orders of magnitude speedup over conventional PT with the same number of replicas. The method applies broadly to constrained Ising problems and can be deployed on existing Ising machines.

cs.LG↗

arXiv2025

Scalable Connectivity for Ising Machines: Dense to Sparse

In recent years, hardware implementations of Ising machines have emerged as a viable alternative to quantum computing for solving hard optimization problems among other applications. Unlike quantum hardware, dense connectivity can be achieved in classical systems. However, we show that dense connectivity leads to severe frequency slowdowns and interconnect congestion scaling unfavorably with system sizes. As a scalable solution, we propose a systematic sparsification method for dense graphs by introducing copy nodes to limit the number of neighbors per graph node. In addition to solving interconnect congestion, this approach enables constant frequency scaling where all spins in a network can be updated in constant time. On the other hand, sparsification introduces new difficulties, such as constraint-breaking between copied spins and increased convergence times to solve optimization problems, especially if exact ground states are sought. Relaxing the exact solution requirements, we find that the overheads in convergence times are milder. We demonstrate these ideas by designing probabilistic bit Ising machines using ASAP7 (a predictive 7nm FinFET technology model) process design kits as well as Field Programmable Gate Array (FPGA)-based implementations. Finally, we show how formulating problems in naturally sparse networks (e.g., by invertible logic) sidesteps challenges introduced by sparsification methods. Our results are applicable to a broad family of Ising machines using different hardware implementations.

cs.ET↗

arXiv2016

All Dielectric Metamaterial Loaded Tunable Plasmonic Waveguide

In this article, a 2D plasmonic waveguide loaded with all dielectric anisotropic metamaterial, consisting of alternative layers of Si-SiO2, has been theoretically proposed and numerically analyzed. Main characteristics of waveguide i.e. propagation constant, propagation length and normalized mode area have been calculated for different values of ridge width and height at telecommunication wavelength. The respective 1D structure of the waveguide has been analytically solved for the anisotropic ridge as a single uniaxial medium with dielectric tensor defined by Effective Medium Theory (EMT). The 2D structure has been analyzed numerically through FEM simulation using Mode analysis module in Comsol Multiphysics. Both the EMT and real multilayer structure have been considered in numerical simulations. Such structure with all dielectric metamaterial provides an extra degree of freedom namely fill factor, fraction of Si layer in a Si-SiO2 unit cell, to tune the propagation characteristics compared to the conventional DLSSP waveguide. A wide range of variations in all the characteristics have been observed for different fill factor values. Besides, the effect of the first interface layer has also been considered. Though all dielectric metamaterial has already been utilized in photonic waveguide as cladding, the implementation in plasmonic waveguide has not been investigated yet to our best knowledge. The proposed device might be a potential in deep sub-wavelength optics, PIC and optoelectronics.

physics.optics↗